• ETRI Journal
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• v.34 no.4
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• pp.485-491
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• 2012

In this paper, the implementations of a $0.1{\mu}m$ gallium arsenide (GaAs) pseudomorphic high electron mobility transistor process for a low noise amplifier (LNA), a subharmonically pumped (SHP) mixer, and a single-chip receiver for 70/80 GHz point-to-point communications are presented. To obtain high-gain performance and good flatness for a 15 GHz (71 GHz to 86 GHz) wideband LNA, a five-stage input/output port transmission line matching method is used. To decrease the package loss and cost, 2nd and 4th SHP mixers were designed. From the measured results, the five-stage LNA shows a gain of 23 dB and a noise figure of 4.5 dB. The 2nd and 4th SHP mixers show conversion losses of 12 dB and 17 dB and input P1dB of -1.5 dBm to 1.5 dBm. Finally, a single-chip receiver based on the 4th SHP mixer shows a gain of 6 dB, a noise figure of 6 dB, and an input P1dB of -21 dBm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.25-33
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• 2007

In this paper, the high isolation and wideband 94 GHz MIMIC(Millimeter-wave Monolithic Integrated Circuit) single balanced cascode mixer was designed and fabricated. Also, we designed and fabricated a 3 dB tandem coupler which has a high isolation and wideband characteristic. The single balanced resistive mixer which does not require an external IF balun was designed using the 0.1 ${\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT(High Electron Mobility Transistor). The DC characteristics of MHEMT's are 665 mA/mm of drain current density, 691 mS/mm of maximum transconductance. The current gain cut-off frequency($f_T$) is 189 GHz and the maximum oscillation frequency($f_{max}$) is 334 GHz. A 94 GHz single balanced cascode mixer was fabricated using our 0.1 ${\mu}m$ MHEMT MIMIC process. From the measurements, the fabricated couplers showed wideband characteristics. The conversion loss of single balanced cascode mixer was 9.8 dB at an LO power of 10.9 dBm. The LO to RF isolation of single balanced cascode mixer was 29.5 dB at 94 GHz. We obtained in this study a higher LO-RF isolation compared to some other single balanced mixers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.1-6
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• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• ETRI Journal
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• v.34 no.5
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• pp.649-654
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• 2012

This paper presents a novel 16-quadrature-amplitude-modulation (QAM) E-band communication system. The system can deliver 10 Gbps through eight channels with a bandwidth of 5 GHz (71-76 GHz/81-86 GHz). Each channel occupies 390 MHz and delivers 1.25 Gbps using a 16-QAM. Thus, this system can achieve a bandwidth efficiency of 3.2 bit/s/Hz. To implement the system, a driver amplifier and an RF up-/down-conversion mixer are implemented using a $0.1{\mu}m$ gallium arsenide pseudomorphic high-electron-mobility transistor (GaAs pHEMT) process. A single-IF architecture is chosen for the RF receiver. In the digital modem, 24 square root raised cosine filters and four (255, 239) Reed-Solomon forward error correction codecs are used in parallel. The modem can compensate for a carrier-frequency offset of up to 50 ppm and a symbol rate offset of up to 1 ppm. Experiment results show that the system can achieve a bit error rate of $10^{-5}$ at a signal-to-noise ratio of about 21.5 dB.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.561-561
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• 2012

Graphene, two dimensional single layer of carbon atoms, has tremendous attention due to its superior property such as fast electron mobility, high thermal conductivity and optical transparency, and also found many applications such as field-effect transistors (FET), energy storage and conversion, optoelectronic device, electromechanical resonators and chemical sensors. Several techniques have been developed to form the graphene. Especially chemical vapor deposition (CVD) is a promising process for the large area graphene. For the electrically isolated devices, the graphene should be transfer to insulated substrate from Cu or Ni. However, transferred graphene has serious drawback due to remaining polymeric residue during transfer process which induces the poor device characteristics by impurity scattering and it interrupts the surface functionalization for the sensor application. In this study, we demonstrate the characteristics of solution-gated FET depending on the removal of polymeric residues. The solution-gated FET is operated by the modulation of the channel conductance by applying a gate potential from a reference electrode via the electrolyte, and it can be used as a chemical sensor. The removal process was achieved by several solvents during the transfer of CVD graphene from a copper foil to a substrate and additional annealing process with H2/Ar environments was carried out. We compare the properties of graphene by Raman spectroscopy, atomic force microscopy(AFM), and X-ray Photoelectron Spectroscopy (XPS) measurements. Effects of residual polymeric materials on the device performance of graphene FET will be discussed in detail.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• ETRI Journal
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• v.42 no.4
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• pp.549-561
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• 2020

We developed a 0.1-㎛ metamorphic high electron mobility transistor and fabricated a W-band monolithic microwave integrated circuit chipset with our in-house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz-108 GHz band and achieved excellent spurious suppression. A low-noise amplifier (LNA) with a four-stage single-ended architecture using a common-source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W-band image-rejection mixer (IRM) with an external off-chip coupler was also designed. The IRM provided a conversion gain of 13 dB-17 dB for RF frequencies of 80 GHz-110 GHz and image-rejection ratios of 17 dB-19 dB for RF frequencies of 93 GHz-100 GHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.120-120
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• 2006

탄소나노튜브는 nm급의 크기에 높은 전기전도도, 열전도 효율, 감한 기계적 강도 등의 장점을 가지며, FED(Field Emission Display), 극미세 전자 스위칭 소자, SET(Single Electron Transistor), AFM(Atomic Force Microscope) tip등 여러 분야로의 응용을 연구하고 있다. 본 연구에서는 탄소나노튜브를 Si 웨이퍼 위에 Ni/Ti 금속층을 촉매층으로 사용하고, 암모니아($NH_3$)가스와 아세틸렌 ($C_2H_2$)가스를 각각 희석가스와 성장원으로 사용하여 합성하였다. 탄소나노튜브의 성장은 Hot filament 화학기상증측(HFPECVD) 방식을 사용하였으며, 이 방법은 다량의 합성, 높은 균일성, 좋은 정렬 특성등의 장점을 가진다. 성장 온도는 탄소나노튜브의 성장 특성을 변화시키는 중요한 요소이다. 성장 온도에 따라 수직적 성장, 성장 밀도등의 특성 변화를 관찰하였다. 성장된 탄소나노튜브층 성분 분석은 에너지 분산형 X-선 측정기(EDS)를 통해 관찰하였고, 끝단에 촉매층이 존재하는 30~50 nm 폭을 가진 다중벽 탄소나노튜브를 고배율 투과전자현미경(HRTEM) 분석을 통해 관찰하였다. 전계방사 주사전자현미경(FESEM) 분석을 동해 1~3${\mu}m$의 길이를 가진 탄소나노튜브가 높은 밀도로 성장된 것을 확인하였다.