• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 추계 기술심포지움 논문집
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• pp.33-36
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• 1999

In this paper, we proposed a simultaneous switching noise(SSN) reduction technique in muti-layer beards(MLB) for high-speed digital applications and analyzed them using the Finite Difference Time Domain(FDTD) method. The new method by conductive dielectric substrates reduces SSN couplings and resonances, significantly, which cause series malfunctions in the modem high-speed digital applications.

• 마이크로전자및패키징학회지
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• 제6권4호
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• pp.9-14
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• 1999

본 논문에서는 고속 디지털 회로에서 발생하는 Simultaneous Switching Noise (SSN)를 감소하기 위한 다층 기판 구조를 제안하고 시간 영역 시간 차분법 (Finite Difference Time Domain Method)을 이용하여 그 효과를 확인하였다. 제안된 구조는 전원 평면과 접지 평면사이에 전도성 유전체를 전체 또는 부분적으로 삽입한 구조로 혼신 전압파의 크기를 각각 최대 85%, 55% 까지 줄일 수 있어 고속 고성능 디지털 시스템 구현에 효과적으로 적용될 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.389-392
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• 1999

It is essential to estimate an effective inductance in a ground plane of muliti-layer IC package system in order to determine the simultaneous switching noise of the package. A new method to estimate the effective ground inductance in multi-layer IC package is presented. With the estimated ground plane inductance values, maximum switching noise variations according to the number of simultaneously switching drivers are investigated by developing a new SSN model. These results are verified by performing HSPICE simulation with the 0.35${\mu}{\textrm}{m}$ CMOS technology.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권3호
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• pp.115-119
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• 2001

This paper presents an efficient and simple method for analyzine maximum simultaneous switching noise (SSN) on ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression, we use ${\alpha}$-power law MOS model and Taylor's series approximation. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that exist some output drivers not in transition.

• 대한전자공학회논문지SD
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• 제39권6호
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• pp.44-50
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• 2002

동시 스위칭 잡음(SSN: Simultaneous Switching Noise)을 줄이기 위한 새로운 기법을 제안한다. 새롭게 제안하는 구조는 이중 층 파워 라인(DLPL: Dual Layer Power Line) 구조를 이용하여 실리콘 상에 상호 인덕터(mutual inductor)를 구현하여 SSN을 줄일 수 있다. 여기서 제안하는 DLPL은 상호 인덕터가 서로 가깝게 위치하여 커플링(coupling)을 높일 수 있으며 순간적인 많은 전류가 서로 반대 방향으로 동시에 흐르게 하여 두 파워 라인 사이에 상호 인덕턴스를 만들어 내며, 이러한 상호 인덕터는 스위칭 잡음을 줄이는 역할을 한다 SPICE 시뮬레이션을 통해 상호 인덕터의 커플링 계수(coupling coefficient)가 0.8 이상일 경우 이전에 보고된 해결 방안들과 비교할 때 63%까지 스위칭 잡음을 더욱 감소 시킬 수 있었다. 또한 이 DLPL 기법은 PCB 회로설계에」=적용시킬 수 있는 이점을 가지고 있다.

• 전자공학회논문지C
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• 제36C권11호
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• pp.55-63
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• 1999

본 논문에서는 패키지의 전기적 특성이 CMOS 디지틀 회로에 미치는 영향을 해석하고 패키지 특성을 고려한 새로운 CMOS It 패키지 설계방법을 보인다. 집적회로 내의 게이트들이 동시에 스위칭 할 때 패키지에 기인한 동시 스위칭 노이즈 (Simultaneous Switching Noise: SSN)가 시스템의 성능에 미치는 영향에 대하여 해석적으로 고찰하여 패키지의 전기적 특성에 의한 제약조건을 만족시키면서 집적회로 패키지를 설계 할 수 있는 새로운 설계 식을 유도하고 이들 식을 이용한 설계방법을 제시한다. 또한 제시된 패키지 설계방 법의 타당성을 검증하기 위하여 0.3㎛ CMOS 회로에 대하여 범용회로 시뮬레이터인 HSPICE 시뮬레이션 결과와 본 논문에서 제시한 해석적 설계 방법에 따른 결과가 일치한다는 것을 보인다.

• 전자공학회논문지
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• 제50권1호
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• pp.97-101
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• 2013

There is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication consists of a master unit (MU) and a slave unit (SU). The MU transmits data to SU using digital optical signals. However, digital optical units that are commercially available or are under development transmit data using two's complement representation. At low input levels, a large number of SSOs (simultaneous switching outputs) are required because of the high rate of bit switching in two's complement, which thereby increases the power noise. This problem reduces the overall system capability because a DSP (digital signal processor) chip (FPGA, CPLD, etc.) cannot be used efficiently and power noise increases. This paper proposes a change from two's complement to a more efficient method that produces less SSO noise and can be applied to existing digital optical units.

• ETRI Journal
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• 제32권2호
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• pp.265-272
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• 2010

To supply a power distribution network with stable power in a high-speed mixed mode system, simultaneous switching noise caused at the multilayer PCB and package structures needs to be sufficiently suppressed. The uni-planar compact electromagnetic bandgap (UC-EBG) structure is well known as a promising solution to suppress the power noise and isolate noise-sensitive analog/RF circuits from a noisy digital circuit. However, a typical UC-EBG structure has several severe problems, such as a limitation in the stop band's lower cutoff frequency and signal quality degradation. To make up for the defects of a conventional EBG structure, a partially located EBG structure with decoupling capacitors is proposed in this paper as a means of both suppressing the power noise propagation and minimizing the effects of the perforated reference plane on the signal quality. The proposed structure is validated and investigated through simulation and measurement in both frequency and time domains.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.129-132
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• 2001

This paper presents an efficient method to estimate the maximum SSN (simultaneous switching noise) for ground interconnection networks in CMOS systems using Taylor's series and analyzes the truncation error that has occurred in Taylor's series approximation. We assume that the curve form of noise voltage on ground interconnection networks is linear and derive a polynomial expression to estimate the maximum value of SSN using $\alpha$-power MOS model. The maximum relative error due to the truncation is shown to be under 1.87% through simulations when we approximate the noise expression in the 3rd-order polynomial.