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SIMULTANEOUS SWITCHING NOISE MINIMIZATION TECHNIQUE USING DUAL LAYER POWER LINE MUTUAL INDUCTORS  

Lee, Yong-Ha (VLSI Design Laboratory, Dept. of Electronic Engineering, Hallym University)
Kang, Sung-Mook (VLSI Design Laboratory, Dept. of Electronic Engineering, Hallym University)
Moon, Gyu (VLSI Design Laboratory, Dept. of Electronic Engineering, Hallym University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.6, 2002 , pp. 44-50 More about this Journal
Abstract
A novel technique for minimization of simultaneous switching noise is Presented. Dual Layer Power Line (DLPL) structure i:; newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly reduce the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.
Keywords
Simultaneous switching noise; SSN; VLSI; Dual Layer Power Line; Noise Minimization;
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  • Reference
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