Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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SIMULTANEOUS SWITCHING NOISE MINIMIZATION TECHNIQUE USING DUAL LAYER POWER LINE MUTUAL INDUCTORS

이중 층 파워 메탈구조의 상호 인덕터를 이용한 동시 스위칭 잡음 최소화 기법

  • Lee, Yong-Ha (VLSI Design Laboratory, Dept. of Electronic Engineering, Hallym University) ;
  • Kang, Sung-Mook (VLSI Design Laboratory, Dept. of Electronic Engineering, Hallym University) ;
  • Moon, Gyu (VLSI Design Laboratory, Dept. of Electronic Engineering, Hallym University)
  • 이용하 (한림대학교 전자공학과 반도체설계연구실) ;
  • 강성묵 (한림대학교 전자공학과 반도체설계연구실) ;
  • 문규 (한림대학교 전자공학과 반도체설계연구실)
  • Published : 2002.06.01
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Abstract

A novel technique for minimization of simultaneous switching noise is Presented. Dual Layer Power Line (DLPL) structure i:; newly proposed for a possible silicon realization of a mutual inductor, with which an instant large current in the power line is half-divided flowing through two different, but closely coupled, layers in opposite directions. This mutual inductance between two power layers enables us to significantly reduce the switching noise. SPICE simulations show that with a mutual coupling coefficient higher than 0.8, the switching noise reduces by 63% compared to the previously reported solutions. This DLPL technique can also be applied to PCB artworks.

동시 스위칭 잡음(SSN: Simultaneous Switching Noise)을 줄이기 위한 새로운 기법을 제안한다. 새롭게 제안하는 구조는 이중 층 파워 라인(DLPL: Dual Layer Power Line) 구조를 이용하여 실리콘 상에 상호 인덕터(mutual inductor)를 구현하여 SSN을 줄일 수 있다. 여기서 제안하는 DLPL은 상호 인덕터가 서로 가깝게 위치하여 커플링(coupling)을 높일 수 있으며 순간적인 많은 전류가 서로 반대 방향으로 동시에 흐르게 하여 두 파워 라인 사이에 상호 인덕턴스를 만들어 내며, 이러한 상호 인덕터는 스위칭 잡음을 줄이는 역할을 한다 SPICE 시뮬레이션을 통해 상호 인덕터의 커플링 계수(coupling coefficient)가 0.8 이상일 경우 이전에 보고된 해결 방안들과 비교할 때 63%까지 스위칭 잡음을 더욱 감소 시킬 수 있었다. 또한 이 DLPL 기법은 PCB 회로설계에」=적용시킬 수 있는 이점을 가지고 있다.

Keywords

References

  1. Y. Yang and J. R. Brews, 'Design Trade-Offs for the Last Stage of an Unregulated, Long-Channel CMOS Off-Chip Driver with Simultaneous Switching Noise and Switching Time Considerations,' IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, VOL. 19, NO. 3, Aug. 1996 https://doi.org/10.1109/96.533886
  2. S. W. Song, M. Ismail, G. Moon, and D. Y. Kim, 'Accurate Modeling of Simultaneous Switching Noise in Low Voltage Digital VLSI,' IEEE International Symposium on Circuits and Systems, Orlando, USA, June, 1999 https://doi.org/10.1109/ISCAS.1999.780132
  3. S. Jou, W. Cheng and Y. Lin, 'Simultaneous Switching Noise Analysis and Low Bouncing Buffer Design,' IEEE 1998 Custom Integrated Circuits Conference, 1998 https://doi.org/10.1109/CICC.1998.695037
  4. C. Spurlin and D. Stein, 'EPIC Advance CMOS Logic Output Edge Control,' Texas Instruments Technical Journal, March-April 1989
  5. A.J.Rainal, 'Computing Inductive Noise of Chip Packages,' AT & T BELL laboratories Technical Journal, pp. 177-195, Jan. 1984
  6. J.D. Irwin, Basic Engineering Circuit Analysis, Prentice Hall International Editions, 1996
  7. 'Simultaneous Switching Noise: Influence of Plane-Plane and Plane-Signal Trace Coupling,' IEEE Transactions on Components, Packaging, and Manufacturing Techology-Part B, VOL. 18, NO.3, Aug. 1995
  8. Yaghmour and J. Prince, 'Effect of Mutual Coupling Between Signal Tracesand Ground Planes on SSO Noise in Packages with Multiple Stacked Ground Planes,' 47th Electronic Components and Technology Conference, pp. 836-841, San Jose, California, May 18-21, 1997 https://doi.org/10.1109/ECTC.1997.606267