• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.438-439
• /
• 2013

Microelectronic devices의 접촉저항의 향상을 위해 Metal silicides의 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 지난 수십년에 걸쳐, Ti silicide, Co silicide, Ni silicide 등에 대한 개발이 이루어져 왔으나, 계속적인 저저항 접촉 소재에 대한 요구에 의해 최근에는 Rare earth silicide에 관한 연구가 시작되고 있다. Rare-earth silicide는 저온에서 silicides를 형성하고, n-type Si과 낮은 schottky barrier contact (~0.3 eV)를 이룬다. 또한, 비교적 낮은 resistivity와 hexagonal AlB2 crystal structure에 의해 Si과 좋은 lattice match를 가져 Si wafer에서 high quality silicide thin film을 성장시킬 수 있다. Rare earth silicides 중에서 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 낮은 schottky barrier 응용에서 쓰이고 있다. 이로 인해, n-channel schottky barrier MOSFETs의 source/drain으로써 주목받고 있다. 특히 ytterbium과 molybdenum co-deposition을 하여 증착할 경우 thin film 형성에 있어 안정적인 morphology를 나타낸다. 또한, ytterbium silicide와 마찬가지로 낮은 면저항과 electric work function을 갖는다. 그러나 ytterbium silicide에 molybdenum을 화합물로써 높은 농도로 포함할 경우 높은 schottky barrier를 형성하고 epitaxial growth를 방해하여 silicide film의 quality 저하를 야기할 수 있다. 본 연구에서는 ytterbium과 molybdenum의 co-deposition에 따른 silicide 형성과 전기적 특성 변화에 대한 자세한 분석을 TEM, 4-probe point 등의 다양한 분석 도구를 이용하여 진행하였다. Ytterbium과 molybdenum을 co-deposition하기 위하여 기판으로 $1{\sim}0{\Omega}{\cdot}cm$의 비저항을 갖는 low doped n-type Si (100) bulk wafer를 사용하였다. Native oxide layer를 제거하기 위해 1%의 hydrofluoric (HF) acid solution에 wafer를 세정하였다. 그리고 고진공에서 RF sputtering 법을 이용하여 Ytterbium과 molybdenum을 동시에 증착하였다. RE metal의 경우 oxygen과 높은 반응성을 가지므로 oxidation을 막기 위해 그 위에 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, 진공 분위기에서 rapid thermal anneal(RTA)을 이용하여 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium silicides를 형성하였다. 전기적 특성 평가를 위한 sheet resistance 측정은 4-point probe를 사용하였고, Mo doped ytterbium silicide와 Si interface의 atomic scale의 미세 구조를 통한 Mo doped ytterbium silicide의 형성 mechanism 분석을 위하여 trasmission electron microscopy (JEM-2100F)를 이용하였다.

• Korean Journal of Materials Research
• /
• v.1 no.4
• /
• pp.191-197
• /
• 1991

The surface roughnesses of titanium silicide films and the diffusion behaviours of dopants in single crystal and polycrystalline silicon substrates durng titanium silicide formation by rapid thermal annealing(RTA) of sputter deposited Ti-filicide film from the composite $TiSi_{2.6}$ target were investigated by the secondary ion mass spectrometry(SIMS), a four-point probe, X-ray diffraction, and surface roughness measurements. The as-deposited films were amorphous but film prepared on single silicon substrate crystallized to the orthorhombic $TiSi_2$(C54 structure) upon rapid thermal annealing(RTA) at $800^{\circ}C$ for 20sec. There was no significant out-diffusion of dopants from both single crystal and polycrystalline silicon substrate into titanum silicide layers during annealing. Most of the implanted dopants piled up near the titanium silicide/silicon interface. The surface roughnesses of titanium silicide films were in the range between 16 and 22nm.

• Transactions on Electrical and Electronic Materials
• /
• v.9 no.4
• /
• pp.137-142
• /
• 2008

The parasitic resistance is studied to silicon/metal contact junction for improving device performance and to lower contact/serial resistance silicide in natural sequence. In this paper constructs the stepwise Ni silicide process for parasitic resistance reduction for silicon/metal contact junction. We have investigated multi-step Ni silicide on SiGe substrate with stepwise annealing method as an alternative to compose more thermally reliable Ni silicide layer. Stepwise annealing for silicide formation is exposed to heating environment with $5^{\circ}C/sec$ for 10 seconds and a dwelling for both 10 and 30 seconds, and ramping-up and the dwelling was repeated until the final annealing temperature of $700\;^{\circ}C$ is achieved. Finally a direct comparison for single step and stepwise annealing process is obtained for 20 nm nickel silicide through stepwise annealing is $5.64\;{\Omega}/square$ at $600\;^{\circ}C$, and it is 42 % lower than that of as nickel sputtered. The proposed stepwise annealing for Ni silicidation can provide the least amount of NiSi at the interface of nickel silicide and silicon, and it provides lower resistance, higher thermal-stability, and superior morphology than other thermal treatment.

• Journal of the Semiconductor & Display Technology
• /
• v.4 no.2 s.11
• /
• pp.7-10
• /
• 2005

[ $SiO_{2}$ ] or SiON is usually deposited and annealed after formation of silicide in real transistor fabrication processes. Nickel silicide and nickel silicide with Co interlayer were annealed at 650$^{\circ}C$ for 30 min with silica top layer in this study to investigate its thermal stability. SEM, XPS, and FPP(four point probe) were employed for the investigation. Nickel silicide with Co interlayer showed improved thermal stability. Co interlayer seems to play a key role to the stability of nickel silicide.

• Korean Journal of Materials Research
• /
• v.4 no.8
• /
• pp.855-860
• /
• 1994

Ta-silicide films in polycide structure were prepared by rapid thermal annealing of sputtered Ta film on poly-Si and doped poly-Si. Effects of phosphorus on Ta-silicide formation were investigated. Independent of the ion dose($1 \times 10^{13}\to 5 \times 10^{15}$/ions/$\textrm{cm}^2$), Ta-silicide phases were formed at $800^{\circ}C$ and stabilized above $1000^{\circ}C$. From the result of XRD at $800^{\circ}C$ and $900^{\circ}C$, however, it was indicated that the more the doping concentration the weaker the intensity of Ta-silicide phases. Furthermore, the observation of SEM revealed that the increase of the doping concentration retarded silicidation. As the temperature increased, the dopant effect was weakened gradually and almost disappeared at $1000^{\circ}C$. Therefore the variation of the ion dose from ($1 \times 10^{13}\to 5 \times 10^{15}$/ions/$\textrm{cm}^2$) did not greatly affect the formation of Ta-silicide at high temperatures but retarded slightly the silicidation at low temperatures.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.1-9
• /
• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.675-678
• /
• 2003

본 논문에서는 N-type 기판에서 Nickel-Silicide를 적용하였을 경우에 나타나는 문제점과 PAI (Pre-amorphization Implant)의 효과에 대하여 알아보았다. N-type 기판에 RTP (Rapid Thermal Process)를 통하여 Nickel-Silicide 를 형성하게 되는데, 여기까지는 안정한 Nickel mono-Silicide (NiSi)가 형성됨을 확인하였다. 하지만 후속 열처리 공정 후 심한 응집 현상 (Agglomeration)과 이상 산화 현상 (Abnormal Oxidation Phenomenon), Silicide Island 등 열안정성 (Thermal Stability) 측면에서 여러 가지 많은 문제점들이 나타났다. 이 후속 열처리의 열안정성 취약점들을 극복하는 방안으로 Ge 및 N₂ PAI를 적용하였다. PAI를 적용하였을 경우에는 그렇지 않은 경우에 비하여 고온 열처리 후에도 면저항이 비교적 잘 유지되었으며, 두께가 얇고 안정한 Nickel-Silicide 특성을 확보할 수 있었다. 특히 Ge PAI 에 비하여 N₂ PAI 의 경우가 보다 특성 개선 효과가 크게 나타났다.

• Korean Journal of Materials Research
• /
• v.14 no.8
• /
• pp.573-578
• /
• 2004

Newly developed silicide materials for ULSI should have the appropriate electrical property of low resistant as well as process compatibility in conventional CMOS process. We prepared $NiCoSi_x$ silicides from 15 nm-Co/15 nm-Ni/Si structure and performed contact dry etch process to confirm the dry etch stability and compatibility of $NiCoSi_x$ layers. We dry etched the photoresist/SiO/silicide/silicon patterns with $CF_4\;and\;CHF_3$ gases with varying powers from 100 to 200 W, and pressures from 45 to 65 mTorr, respectively. Polysilicon and silicon active layers without silicide were etched $0\sim316{\AA}$ during over etch time of 3min, while silicon layers with proposed $NiCoSi_x$ silicide were not etched and showed stable surfaces. Our result implies that new $NiCoSi_x$ silicides may replace the conventional silicides due to contact etch process compatibility.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.1
• /
• pp.29-34
• /
• 2008

In this paper, we investigated electrical and physical characteristics of nickel silicide using rare-earth metals(Er, Yb, Tb, Dy), Incorporated Ytterbium into Ni-silicide is proposed to reduce work function of Ni-silicide for nickel silicided schottky barrier diode (Ni-silicided SBD). Nickel silicide makes ohmic-contact or low schottky barrier height with p-type silicon because of similar work function (${\phi}_M$) in comparison with p-type silicon. However, high schottky barrier height is formed between Ni-silicide and p-type substrate by depositing thin ytterbium layer prior to Ni deposition. Even though the ytterbium is deposited below nickel, ternary phase $Yb_xN_{1-x}iSi$ is formed at the top and inner region of Ni-silicide, which is believed to result in reduction of work function about 0.15 - 0.38 eV.

• Journal of the Korean institute of surface engineering
• /
• v.30 no.6
• /
• pp.374-381
• /
• 1997

We have studied the effect of the interface between tungsten silicide and polysilicon the silicide reaction. The results showed that the cleaning of the silicon surface prior to the deposition of tungsten silicide affected the interface properties, thereby leading to the difference in the resistivity and surface morhpology of tungsten silicide. Compared with HF cleaning, the use of SCl cleaning yielded higher resistivity of tungsten silicide at the low anneal temperature (up to $900^{\circ}C$). However, furtherature to $1000^{\circ}C$ reduced the resistivity significantly, similar to that obtained with HF cleaning. It was also observed that the annealing of WSix/HF-cleaned poly-si allowed the formation of bucking weve (partially decohesion area) on the surface. In contrast, the use of SCl celaning did not produce the buckling waves on the surface. Also the presence of 200$\AA$ -thick TiW between tungsten silicide and HF-cleaned poly-Si effectively prevented the formation of the waves. However, high-temperature annealing of WSix/200A-TiW/Poly-Si allowed the excess silicon in tungsten silicide to precipitate inside the silcide, causing the slight increase of the resistivity after annealing at $1050^{\circ}C$.