• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.3
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• pp.186-190
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• 2005

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics, 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB\~-0.63LSB$ and $0.53LSB\~-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Journal of Electrical Engineering and Technology
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• v.8 no.4
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• pp.951-958
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• 2013

This paper proposes the controller design for a stability improvement of an on-board battery charger. The system is comprised of a power factor correction (PFC) circuit and phase shift full-bridge DC-DC converter. The PFC circuit performs the control of the DC-link voltage and the input power factor. The DC-DC converter regulates the voltage and the current in the battery using the DC-link voltage. This paper proposes the design method of PI controller for the PFC circuit using a small signal model. The analysis and design of a type-three controller for the DC-DC converter is also presented. A simulation and experiment has been performed on the on-board battery charger and their results are presented to verify the validity of the proposed system.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.2
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• pp.123-130
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• 2007

This paper presents the generalized and explicit expressions for evaluating the performance of the multi-phase interleaved buck converter (IBC) operating in discontinuous inductor current mode (DICM). The full-order averaged model is derived. The generalized transfer functions of interest are presented and the dynamic characteristics are analyzed. The generalized analysis of converter performance is verified through the experimental and simulation results.

• Proceedings of the KIPE Conference
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• 2008.10a
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• pp.45-47
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• 2008

This paper describes development of PMSG wind power system model using wind turbine simulator and matrix converter. The wind turbine simulator, which consists of an induction motor with vector drive, calculates the output torque of a specific wind turbine using simulation software and sends the torque signal to the vector drive after scaling down the calculated value. The operational feasibility of interconnected PMSG system with matrix converter was verified by computer simulations with PSCAD/EMTDC software. The simulation results confirm that matrix converter can be effectively applied for the PMSG system.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.209-211
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• 1995

This paper is concerned with High Frequency, High Voltage Generator for X-ray using zero-voltage soft-switching PWM DC-DC high-power converter by Resonant method, which makes the most of the parastic LC parameters of high-voltage transformer link, for diagnostic X-ray power generator. The converter circuit basically utilizes phase-shift pulse width modulated series Resonant full-bridge PWM DC-DC high-power converter operating at a constant frequency;25kHz. The converter output regulation is digitally controlled using DSP (Digital Signal Processor) for obtaining a fast rising time and adjust output voltage within a wide load range.

• Journal of Biomedical Engineering Research
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• v.16 no.3
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• pp.301-308
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• 1995

A high-precision pre-amplifier is designed for general use in EEG measurement system. It consists of signal generator, signal amplifier with a impedance converter, shield driver, body driver, differential amplifier, and isolation amplifier. The combination of minimum use of inaccurate passive components and the appropriate matching of each monolithic amplifiers results in good noise behavior, low leakage current, high CMRR, high input impedance, and high IMRR. The performance of EEG pre-amplifier has been verified by showing the typical EEG pattevn of a nomad person through the clinical experiments.

• Journal of IKEEE
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• v.22 no.2
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• pp.514-517
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• 2018

In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive-approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.

• Journal of Power Electronics
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• v.12 no.3
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• pp.410-417
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• 2012

In this paper, a direct current control method based on a one-cycle controller (DCOCC) for double frequency buck converters (DF buck) is proposed. This control method can make the average current through the high frequency and low frequency inductors of a DF buck converter equal. This is similar to the average current control method. However, the design of the loop compensator is much easier when compared with the average current control. Since the average current though the high frequency and low frequency inductors is equivalent, the current stress of the high frequency switches and the switch losses are minimized. Therefore, the efficiency of the DF buck converter is improved. Firstly, the operation principle of DCOCC is described, then the small signal models of a one cycle controller and a DF buck converter are presented based on the state space average method. Eventually, a system block diagram of the DCOCC controlled DF buck is established and the compensator is designed. Finally, simulation and experiment results are given to verify the correction of the theory analysis.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.355-358
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• 2010

As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.