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http://dx.doi.org/10.5370/KIEE.2010.59.2.355

A 12-bit 1MS/s SAR ADC with Rail-to-Rail Input Range  

Kim, Doo-Yeoun (고려대학교 마이크로/나노협동과정)
Jung, Jae-Jin (고려대학교 전기전파공학과)
Lim, Shin-Il (서경대학교 컴퓨터공학과)
Kim, Su-Ki (고려대학교 전기전자전파공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.59, no.2, 2010 , pp. 355-358 More about this Journal
Abstract
As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is $0.6mm^2$.
Keywords
Successive Approximation Register (SAR); ADC; Rail-to-Rail; DNW; Split capacitor;
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