• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.10-11
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• 2006

In this study, the Ni/Co/TiN (6/2/25 nm) structure was deposited for thermal stability estimation. Vacuum (30 mTorrs) annealing was carried out to compare with furnace annealing in nitrogen ambient. The proposed Ni/Co/TiN structure exhibited low temperature silicidation and wide range of rapid thermal process (RTP) windows. The sheet resistance was too high to measure after furnace annealing at $600^{\circ}C$ due to the thin thickness (15 nm) of the nickel silicide. However, the sheet resistance maintained stable characteristics up to $600^{\circ}C$ for 30 min after vacuum annealing. Therefore, the low resistance of thin film nickel silicide was obtained by vacuum annealing at $600^{\circ}C$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.500-501
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• 2005

Aluminum doped zinc oxide films (ZnO:Al) were deposited on glass substrate by DC magnetron sputtering from a ZnO target mixed with 2 wt% $Al_2O_3$. The effects of substrate bias on the electrical properties and film structure were studied. Films deposited with positive bias have been annealed at $600^{\circ}C$ using rapid thermal anneal (RTA) process. The effects of RTA on the evolution of film microstructure are to be also studied using X-ray diffraction, transmission electron microscopy, and atomic force microscopy. Positive bias sputtering may induce lattice defects caused by electron bombardments during deposition. The as-deposited film microstructure evolves from the film with high defect density to more stable film condition. The electrical properties of the films after RTA process were also studied and the results were correlated with the evolution of film microstructures.

• Journal of the Korean Vacuum Society
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• v.13 no.2
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• pp.72-78
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• 2004

Cu seed layers deposited by magnetron sputtering onto tantalum nitride barrier films were treated with ECR plasma and then the copper films were electroplated and rapid thermal annealed in an argon or nitrogen atmosphere at various temperatures ranging from 200 to $500^{\circ}C$. Changes in the microstructure and physical properties of the copper films electroplated on the hydrogen ECR plasma cleaned copper seed layers were investigated using X-ray diffraction (XRD), electron back-scattered diffraction (EBSD), and atomic force microscopy (AFM) analyses. It was found that the copper film undergoes complete recrystallization during annealing at a temperature higher than $400^{\circ}C$. The resistivity of the Cu film tends to decrease and the degree of (111) preferred orientation tends to increase as the annealing temperature increases. Theoptimum annealing condition for obtaining the film with the lowest resistivity, the smoothest surface and the highest degree of the (111) preferred orientation is rapid thermal annealing in a nitrogen atmosphere at $400^{\circ}C$ for 120 s. The resistivity and the surface roughness of the electroplated copper film annealed under this condition are 1.98 $\mu$O-cm and 17.77 nm, respectively.

• Journal of the Korean Ceramic Society
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• v.36 no.6
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• pp.604-610
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• 1999

Silicide layer structures and morphology degradation of the surface and interface of the silicide layers for he Co/refractory metal bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The CoSi-CoSi2 phase transition temperature is lower an morphology degradation of the silcide layer occurs more severely for the Co/refractorymetal bilayer on the P-doped polycrystalline Si substrate than on the single Si substrate. Also the final layer structure and the morphology of the films after silicidation annealing was found to depend strongly upon the interlayer metal. The layer structure after silicidation annealing of Co/Hf/doped-poly Si is Co-Hf alloy/polycrystalline CoSi2/poly Si substrate while that of Co/Nb is polycrystalline CoSi2/NbSi2/polycrystalline CoSi2/poly Si.

• Electrical & Electronic Materials
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• v.10 no.9
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• pp.881-888
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• 1997

This study demonstrats the profiles of phosphorus ions in silicon by MeV implantation(1∼3 MeV). Implanted profiles could be measured by SIMS(Cameca 4f) and compared with simulation results(TRIM program and analytical description method only using on Pearson function). The experimental result in the peak concentration region has a little bit deviation from simulation data. By RBS and Channeling measurements the defect distribution of implanted samples could be measured and spectrum are calibrated depth with RUMP simulation By XTEM measurement the thickness of defect zone also could be measured. Finally thermal annealing for the electrical activation of implanted ions carried out by RTA(rapid thermal annealing). The concentration-depth profiles after heat treatment was measured by SR(spreading resistance)-method.

• Korean Journal of Materials Research
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• v.16 no.5
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• pp.292-296
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• 2006

Effects of rapid thermal annealing of bismuth telluride thin films on their thermoelectric properties were investigated. Films with four different compositions were elaborated by co-sputtering of Bi and Te targets. Rapid thermal treatments in range of $300{\sim}400^{\circ}C$ were carried out during 10 minutes under the reducing atmosphere (Ar with 10% $H_2$). As the temperature of thermal treatment increased, carrier concentrations of films decreased while their mobilities increased. These changes were clearly observed for the films close to the stoichiometric composition. Rapid thermal treatment was found to be effective in improving the thermoelectric properties of $Bi_2Te_3$ films. Recrystallization of $Bi_2Te_3$ phase has caused the enhancement of thermoelectric properties, along with the decrease of the carrier concentration. Maximum values of Seebeck coefficient and power factor were obtained for the films treated at $400^{\circ}C$ (about $-128{\mu}V/K$ and $9{\times}10^{-4}\;W/K^2m$, respectively). With further higher temperature ($500^{\circ}C$), thermoelectric properties deteriorated due to the evaporation of Te element and subsequent disruption of film's structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.7
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• pp.708-712
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• 2004

Shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes. The dopant implantation was performed into the crystalline substrates using BF$_2$ ions. The annealing was performed with a rapid thermal processor and a furnace. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of junction depth and sheet resistance. A new simulator is designed to model boron diffusion in silicon. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. Using initial conditions and boundary conditions, coupled diffusion equations are solved successfully. The simulator reproduced experimental data successfully.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.7
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• pp.415-418
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• 2015

In this paper, $TiO_2$ based thin-film transistors (TFTs) were fabricated using by an atomic layer deposition with high aspect ratio and excellent step coverage. $TiO_2$ semiconducting layer was deposited showing a rutile phase through the rapid thermal annealing process, and exhibited TFT characteristics with a $200{\mu}m$ channel length of low-leakage currents (none of current flow during off-state), stable threshold voltages (-10 V ~ 0 V), and a much higher on/off current ratio (<$10^5$), respectively.

• Proceedings of the Optical Society of Korea Conference
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• 2009.02a
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• pp.525-526
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• 2009

we investigated the effect of rapid thermal annealing (RTA) temperature on photoluminescence (PL) of 635 nm InGaP/InGaAlP multiple quantum well structure. RTA is performed with the quantum well structure with 5.5 nm of well width. The highest PL peak intensity is shown at 1 min. of RTA at $720^{\circ}C$ sample as 3 times higher as compared to the as-grown sample. The effect may be assigned to an expected reduction in number of nonradiative recombination centers in the quantum well.