• Journal of Navigation and Port Research
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• v.27 no.1
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• pp.81-86
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• 2003

In the paper, the power amplifier using active biasing for LDMOS MRF-21060 is designed and fabricated. Driving amplifier using AH1 and parallel power amplifier AH11 is made to drive the LDMOS MRF 21060 power amplifier. The variation of current consumption in the fabricated 5 Watt power amplifier has an excellent characteristics of less than 0.1A, whereas passive biasing circuit dissipate more than 0.5A. The implemented power amplifier has the gain over 12 dB, the gain flatness of less than $\pm$0.09dB and input and output return loss of less than -19dB over the frequency range 2.11~2.17GHz. The DC operation point of this power amplifier at temperature variation from $0^{\circ}C$ to $60^{\circ}C$ is fixed by active circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.1
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• pp.15-22
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• 1977

We have obtained a violet-sensitive photocell as a part of the developing project on such type of solar cell. The photocell has the structure of SnO2-SiO2-Si MOS coupled on Si n-p homojuction. It is not relevant to use as a solar cell because of its small photovoltaic power(0.25V, 150$mutextrm{A}$), however, since the spectral response of the cell is shifted toward the violet band region and its switching speed is fairly high in comparison with those of the Si p-n homojunction type solar cell, it is expected that we will be able to find mere novel utilities than the ordinary silicon photocell.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.2
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• pp.71-78
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• 2017

In This Paper, A DC-DC Boost Converter for Portable Device has been Proposed. The Converter Which is Operated with 1 MHz High Switching Frequency is Capable of Reducing Mounting Area of Passive Devices Such as Inductor and Capacitor, Consequently is Suitable for Portable Device. This Boost Converter Consists of a Power Stage and a Control Block and a Protect Block. Proposed DC-DC Boost Converter has been Designed a 0.18 um Magnachip CMOS Process Technology, we Examined Performances of the Fabricated Chip and Compared its Measured Results with SPICE Simulation Data. Simulation Results Show that the Output Voltage is 4.8 V in 3.3 V Input Voltage, Output Current 95 mA Which is Larger than 20~50 mA.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.212-214
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• 2005

The charge-pump circuit which is used to generate higher voltage than the available supply voltage has wide applications such as the flash memory of EEPROM Because the demand for high voltage comes from physical mechanism such as the oxide tunneling, the required pumped voltage cannot be scaled as the power supply voltage is scaled. Therefore, an efficient charge-pump circuit that can achieve high voltage from the available low supply voltage is essential. A new Analog Switch p-well CMOS charge pump circuit without the MOS device body effect is processed. By improve the structure of the circuit's transistors to reduce the threshold voltage shift of the devices, the threshold voltage of the device is kept constant. So, the circuit electrical characteristics are higher output voltage within a shorter time than the conventional charge pump. The propose analog switch CMOS charge pump shows compatible performance of the ideal diode or Dickson charge pump.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.185-196
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• 2002

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

• Journal of Sensor Science and Technology
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• v.17 no.1
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• pp.41-52
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• 2008

In this paper, a circuit analysis of the complementary CMOS active pixel and readout circuit is carried out. Complementary pixel structure which is different from conventional 3TR APS structure is consist of photo diode, reset PMOS, several NMOSs and PMOSs sets for complementary signals. Photo diode is modelled with Medici device program. HSPICE was used to analyze the variation of the signal feature depending on light intensity using $0.5{\mu}M$ standard CMOS process. Simulation results show that the output signal range is from 0.8 V to 4.5 V. This signal range increased 135 % output dynamic range compared to conventional 3TR pixel in the condition of 5 V power supply.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.118-123
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• 1989

In this paper, as we have integrated SCF for voice signal processing using CMOS circuit with the low power dissipation and the easy circuit design, it has been presented the simplified CMOS OP AMP design method with ${\pm}$5V pwoer source in order to use together with digital part. After an example about SCF CMOS OP AMP design, it has been performed layout appling channel width and length obtained by design method, and then its characteristics were simulated by SPICE 2G program. Therefoe, this design method will be applied the general CMOS OP AMP design in the electronic circuit.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.941-943
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• 1999

In this paper, the AC breakdown properties to investigate the electrical properties of gate oxide layer in MOSFET was studied. 5 inch arsenic epi-wafer is selected as an experimental specimen, the power MOSFET of a general MOS structure was made. In order to analyze the physical properties of the specimen, the SIMS(secondary ion mass spectroscopy) was used. As the experimental condition, the experiment al of the AC breakdown characteristics was performed when the thickness of gate oxide layer is $600[\AA]$ and $800[\AA]$, the resistivity is $1.2[\Omega{\cdot}cm]$, $1.5[\Omega{\cdot}cm]$ and $1.8[\Omega{\cdot}cm]$, and the diffusion time is 110[min] and 150[min] in temperature $30[^{\circ}C]{\sim}100[^{\circ}C]$. From the analysis result of the SIMS spectrum, it is confirmed that the dielectric strength is decreased by contribution of the impurities ad dition as increasing in thickness of the gate oxide layer in MOSFET.