• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.370-375
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• 1986

In this paper, modeling of the conduction mechanism of ion implanted p-type polycrystalline silicon is studied. From this modeling, the resistivity of p-type polycrystalline and its dependence on dopant concentration are calculated. The proposed modeling whose grain size is about 1450 \ulcorneris shwon to agree well with the experimental result.

• 한국신재생에너지학회:학술대회논문집
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• 2010.06a
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• pp.96.2-96.2
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• 2010

The surface morphology and structural properties of polycrystalline silicon (poly-Si) films made in-situ aluminum induced crystallization at various substrate temperature (300~600) was investigated. Silicon films were deposited by hot-wire chemical vapor deposition (HWCVD), as the catalytic or pyrolytic decomposition of precursor gases SiH4 occurs only on the surface of the heated wire. Aluminum films were deposited by DC magnetron sputtering at room temperature. continuous poly-Si films were achieved at low temperature. from cross-section TEM analyses, It was confirmed that poly-Si above $450^{\circ}C$ was successfully grown on and poly-Si films had (111) preferred orientation. As substrate temperature increases, Si(111)/Si(220) ratio was decreased. The electrical properties of poly-Si film were investigated by Hall effect measurement. Poly-Si film was p-type by Al and resistivity and hall effect mobility was affected by substrate temperature.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.3 no.1
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• pp.59-65
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• 1993

The boron-doped polycrystalline silicon films which can be used in pressure sensors were fabricated in a high-vacuum resistance heating evaporator. Poly-Si films were deposited on quartz substrates at various temperatures and the boron was doped to the silicon film in a diffusion furnace using BN wafer. The silicon films deposited at $500^{\circ}C$ was amorphous, began to show crystalline at $600^{\circ}C$, and became polycrystalline at $700^{\circ}C$. After doping boron at $900^{\circ}C$for 10 minutes, the resistivity of the films was in the range of $0.1{\Omega}cm~1.5{\Omega}cm$, the boron density was $9.4\times10^{15}~2.1\times{10}^{17}cm^{-3}$, and the grain size was $107{\AA}~191{\AA}$.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.95-96
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• 2009

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.2
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• pp.121-126
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• 2004

In this paper, the effects of the ozone oxidation of the landing polycrystalline silicon on the cell contact resistance of the DRAM device were studied. For this study, the ozone oxidation of the landing polycrystalline silicon layer was performed under various conditions, which was followed by the normal DRAM processes. Then, the cell contact resistance and $t_{WR}$ (write recovery time) of the devices were measured and analyzed. The experimental results showed that the cell contact resistance was more significantly increased for higher temperature of oxidation, longer time of oxidation, and higher concentration of ozone in the oxidation furnace. In addition, the TEM cross-sectional micrographs clearly showed that the oxide layer at the interface between the landing polycrystalline silicon layer and the plug polycrystalline silicon layer was increased by the ozone oxidation. Furthermore, the rate of the device failure due to too large write recovery time was also found to be well correlated with the increase of the cell contact resistance.

• Analytical Science and Technology
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• v.24 no.2
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• pp.105-112
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• 2011

Syntheses and property analysis of hydropolysilanes were studied. Those hydropolysilanes can be utilized as precursors for amorphous silicon and polycrystallline silicon for the purpose of the solar cell and the thin film transister for the next generation's semiconductors. Most important characteristics of this study are to find optimized conditions for the synthesis and property analysis of soluble hydropolysilanes. Also the possibility of pyrolytic conversion to amorphous and polycrystalline silicon was investigated.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.129-134
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• 2004

The development of fabrication processes of polycrystalline-silicon-thin-film transistors (poly-Si TFTs) at low temperatures is reviewed. Rapid crystallization through laser-induced melt-regrowth has an advantage of formation of crystalline silicon films at a low thermal budget. Solid phase crystallization techniques have also been improved for low temperature processing. Passivation of $SiO_2$/Si interface and grain boundaries is important to achieve high carrier transport properties. Oxygen plasma and $H_2O$ vapor heat treatments are proposed for effective reduction of the density of defect states. TFTs with high performance is reported.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.4 no.2
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• pp.111-118
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• 1994

Silicon single crystals were continuously grown by a modified process. Polycrystalline silicon powder was fed from the top reservoir to the growth chamber. Silicon single crystals were grown from the botton of the growth chamber. The balance between the gravitational force of melt and the centrifugal force originated from the rotation of seed was the one of the main factors to control the diameter of crystals grown and quality, etc.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.