• Proceedings of the IEEK Conference
• /
• 2000.06b
• /
• pp.322-325
• /
• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1015-1018
• /
• 2004

We proposed a new cross-coupled level shifter circuit using low temperature poly-Si(LTPS) TFT. The proposed level shifter can operate on low input voltage in spite of low mobility and widely varying high threshold voltage of LTPS TFT. Also, the proposed level shifter operates at high frequency and reduces power consumption for having fast rising and falling time and shortening period flowing short-circuit currents.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1266-1269
• /
• 2007

Polycrystalline silicon (poly-Si) films were prepared directly on plastic substrates at a low (< $200^{\circ}C$) by using Catalytic Chemical Vapor Deposition (Cat-CVD) technique without subsequent annealing steps. Surface roughness of the poly-Si layer and the density of the gate dielectric layer were found to be influential to the TFT performance.

• Proceedings of the KIEE Conference
• /
• 2002.11a
• /
• pp.71-73
• /
• 2002

본 연구에서는 TFT-LCD 의 동작특성을 정확하게 계산하기 위해 준 실험적인 TFT 모델을 사용하여 a-Si TFT poly-Si TFT, Organic TFT에 대하여 파라미터를 추출하였다. 이렇게 추출된 TFT의 파라미터를 TFT-LCD 등가회로에 적용하여 화소의 동작 특성에 관하여 연구하였다. 또한 보다 정확한 시뮬레이션을 위하여 VLSI분야에서 사용되는 준 실험적인 정정용량 모델과 액정의 특성과 인가된 전압에 의존하는 액정 용량모델들을 사용하여 화소의 충 방전 특성을 시뮬레이션 하였는데 대면적 고화질의 패널일수록 특성이 우수한 TFT가 적용되어야 하며, 유기 TFT를 TFT-LCD에 적용시키기 위하여 유기 TFT의 성능향상 및 고전압의 구동방식이 필요하게 된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.10
• /
• pp.918-923
• /
• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.1162-1165
• /
• 2006

In this paper, the characteristics of polycrystalline silicon thin-film transistors (poly- Si TFTs) fabricated on polymer substrates are investigated. The a-Si films was laser annealed by using a XeCl excimer laser and a four-mask-processed poly-Si TFT was fabricated with fully self-aligned top gate structure. The fabricated nMOS TFT showed field-effect mobility of ${\sim}30\;cm^2/Vs$, on/off ratio of $10^5$ and threshold voltage of 5 V.

• Journal of Information Display
• /
• v.8 no.4
• /
• pp.15-18
• /
• 2007

In this paper, we investigated the SLS process to control grain boundary(GB) location in TFT channel region, and it has been found to be applicable for locating the GB at the same location in the channel region of each TFT. We fabricated TFT by applying a new alignment SLS process and compared the TFT characteristics with a normal SLS method and the grain boundary location controlled SLS method. Also, we have analysed degradation phenomena under hot carrier stress conditions for n-type LDD MOSFETs.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.261-264
• /
• 1999

This paper presents a circuit-level method to deal with transistor nonuniformity In this method, which is called transistor slicing, a transistor is implemented as a parallel connection of multiple smaller transistors. The paper analyzes the method and demonstrates that transistor slicing can effectively reduce the nonuniformity in TFT mobility and threshold voltage. The method is particularly useful in Implementing analog functions using poly-silicon TFTs which show a significant level of nonuniformity.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.11
• /
• pp.969-975
• /
• 2002

Thin film transistors(TFT) were made based on the polycrystalline Si (poly-Si) crystallized by sequential lateral solidification(SLS) method. The electrical characteristics of the devices were analyzed. n-type TFTs did not show a superior characteristics compared to p-type TFTs. We analyzed the causes of the failure by focused ion beam(FIB) analysis and automatic spreading resistance(ASR) measurement, to study the structural integrity and the doping distribution, respectively. FIB showed no structural problems but it revealed a non-intermixed layer in the contact holes between the polysilicon and the aluminum electrode. ASR analyses on poly-Si layer with various doping concentrations and activation temperatures showed that the inadequately doped areas were partially responsible for the inferior behavior of the whole device.

• Information Display
• /
• v.4 no.1
• /
• pp.30-35
• /
• 2003