• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.74-80
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• 2006

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise performance. The proposed PLL has two Charge Pump (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppress the voltage fluctuation of LF. In result, it improves phase noise characteristic. The Proposed PLL has been fabricated with 0.35fm 3.3V CMOS process. Measured phase noise at 1-MHz offset is -103dBc/Hz resulting in a minimum 3dBc/Hz phase noise improvement compared to the conventional PLL.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.807-813
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• 2009

A Satellite transponder is the Communication system to process signal with up-link signal recovery, and transmit to ground station through down-link. The orbit flight in the deep space causes high doppler shift in the received signals from the ground station so that the Carrier recovery and fast synchronization system are essential for the transponder system. The conventional analog transponder is employing the system's carrier recovery along with the PLL (Phase Locked Loop) designed for satellite's operation. This paper presents a digital carrier recovery scheme which can provide more reliable and software reconfigurable implementation technique for satellite transponder system without verifying scheme along with transponder designed for short distance or deep space satellite.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.586-591
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• 2000

In this paper, a PLHRO(Phase Locked Hair-pin Resonator Oscillator) for K-band is designed with the feedback property of PLL(Phase Locked Loop) using a new tuning mechanism. The proposed PLHRO generates the output power of -0.6 dBm at 24.42 GHz, and has the phase noise of -86.6 dBc/Hz at 100 KHz and -76.5 dBc/Hz at 10KHz offset from carrier frequency, and has suppression characteristics of -23 dBc and spurious noise of -65 dBc. Buffered 24.42 GHz PLHRO generates the output power of 5.6 dBm at 24.42 GHz and has the of a phase noise of -77.34 dBc/Hz at 100 KHz and -72 dBc/Hz at 100 KHz offset from carrier frequency.

• Journal of Advanced Navigation Technology
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• v.2 no.1
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• pp.22-33
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• 1998

In the coherent-on-receiver radar system using the magnetron source, frequency synthesizer is employed as a STALO(Stable Local Oscillator) to keep the intermediate frequency stable. In this paper, X-band(8.4GHz~9.7GHz) single loop frequency synthesizer is designed and implemented by an indirect frequency synthesis technique. Phase comparison is performed by a digital PLL(Phase-Locked Loop) chip and the loop filter is designed for the low phase noise. The effects of loop component characteristics on the output phase noise are analyzed for single loop structures, and the calculated results are compared with the measured data.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.71-76
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• 2010

In this paper, a 120 GHz local oscillator(LO) for the sub-harmonic mixer in the THz transceiver with a carrier frequency of 240 GHz was designed and fabricated. A 120 GHz local oscillator was composed of 40 GHz PLL(Phase Locked Loop), 40 GHz BPF(Band Pass Filter), frequency tripler and 120 GHz BPF. The commercial model of the frequency tripler was used. The measured result of the 40 GHz PLL showed the phase noise of -105 dBc/Hz at the 100 kHz offset frequency. The measured result of 120 GHz BPF showed the insertion loss of 1.3 dB at center frequency of 119 GHz with bandwidth of 5 GHz. The output power of 120 GHz LO was measured to 6.6 dBm.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.3
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• pp.106-113
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• 1997

In uninterruptible power supply(UPS), a high speed phase control is usually required to compensate transients in the output voltage at the instant of transfer from the ac line to the inverter when the ac line fails or backs to the ac line in case of the inverter fails. To overcome this problem, this paper pre¬sents the closed digital phase-locked loop(DPLL) techniques designed by full software with TMS320C31 digital signal processor and describes the functional operation of the proposed DPLL. Fi¬nally, the performance of the proposed DPLL is shown and discussed through simulation and experiment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.2
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• pp.194-200
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• 2003

In this paper, FSK(Frequency Shift Keying) demodulator which is widely used for FH-SS system is designed and the experimental results are analyzed. The performance of the ADPLL(All-digital Phase-Locked-Loop), which is the main part of the demodulator circuit, is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the ADPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. There is about 2${\mu}\textrm{s}$ difference in time constant of the PLL. This difference is not critical in the demodulator. And the experimental results show that the transmitted data is well demodulated when the phase difference between the FSK modulated signal and the reference signal is about 180 degree.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.11
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• pp.1447-1454
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• 2018

In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.9
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• pp.1692-1701
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• 1994

Macromodeling technology is useful to simulate and analyze the performance of new elements and complicated circuits or systems without any changes in today's general simulator, PSPICE. In this paper, Phase Locked Loop(PLL) is designed using macromodeling technique. The PLL macromodel has two basic sub-macromodels of the phase detector and the voltage controlled oscillator(VCO). The PLL macromodel has two open terminals for inserting RC low pass filter. The PLL macromodel is simulated using simulation parameters of LM565CN manufactured in the National company. At a free-running frequency, 2500Hz, upper lock range and lower capture range was 437Hz, 563Hz, respectively. Also, experimental results and simulation results of LM565CN PLL show good agreement.