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Analysis and design of a FSK Demodulator with Digital Phase Locked Loop  

김성철 (우송대학교 컴퓨터ㆍ전자정보공학부)
송인근 (우송대학교 컴퓨터ㆍ전자정보공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.7, no.2, 2003 , pp. 194-200 More about this Journal
Abstract
In this paper, FSK(Frequency Shift Keying) demodulator which is widely used for FH-SS system is designed and the experimental results are analyzed. The performance of the ADPLL(All-digital Phase-Locked-Loop), which is the main part of the demodulator circuit, is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the ADPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. There is about 2${\mu}\textrm{s}$ difference in time constant of the PLL. This difference is not critical in the demodulator. And the experimental results show that the transmitted data is well demodulated when the phase difference between the FSK modulated signal and the reference signal is about 180 degree.
Keywords
FS-SS system; ADPLL; FSK demodulator; time constant;
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