• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.94-94
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• 2008

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• 전자공학회논문지A
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• 제30A권2호
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• pp.53-63
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• 1993

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

• 한국전기전자재료학회논문지
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• 제24권11호
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.382.1-382.1
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• 2014

Graphene field-effect transistors (GFET) is one of candidates for future high speed electronic devices since graphene has unique electronic properties such as high Fermi velocity (vf=10^6 m/s) and carrier mobility ($15,000cm^2/V{\cdot}s$) [1]. Although the contact property between graphene and metals is a crucial element to design high performance electronic devices, it has not been clearly identified. Therefore, we need to understand characteristics of graphene/metal contact in the GFET. Recently, it is theoretically known that graphene on metal can be doped by presence of interface dipole layer induced by charge transfer [2]. It notes that doping type of graphene under metal is determined by difference of work function between graphene and metal. In this study, we present the GFET fabricated by contact metals having high work function (Pt, Ni) for p-doping and low work function (Ta, Cr) for n-doping. The results show that asymmetric conductance depends on work function of metal because the interfacial dipole is locally formed between metal electrodes and graphene. It induces p-n-p or n-p-n junction in the channel of the GFET when gate bias is applied. In addition, we confirm that charge transfer regions are differently affected by gate electric field along gate length.

• 센서학회지
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• 제28권2호
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• pp.76-80
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• 2019

The characteristics of a titanium oxide layer prepared using a plasma electrolytic oxidation (PEO) process were investigated, using an extended gate ion sensitive field effect transistor (EG-ISFET) to confirm the layer's capability to react with hydrogen ions. The surface morphology and element distribution of the PEO-processed titanium oxide were observed and analyzed using field-emission scanning-electron microscopy (FE-SEM) and energy-distribution spectroscopy (EDS). The titanium oxide prepared by the PEO process was utilized as a hydrogen-ion sensing membrane and an extended gate insulator. A commercially available n-channel enhancement MOS-FET (metal-oxide-semiconductor FET) played a role as a transducer. The responses of the PEO-processed titanium oxide to different pH solutions were analyzed. The output drain current was linearly related to the pH solutions in the range of pH 4 to pH 12. It was confirmed that the titanium-oxide layer prepared by the PEO process could feasibly be used as a hydrogen-ion-sensing membrane for EGFET measurements.

• ETRI Journal
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• 제25권3호
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• pp.203-209
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• 2003

This paper reports on our investigation of DC and RF characteristics of p-channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained $Si_{0.8}Ge_{0.2}$ channel. Because of enhanced hole mobility in the $Si_{0.8}Ge_{0.2}$ buried layer, the $Si_{0.8}Ge_{0.2}$ pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the $Si_{0.8}Ge_{0.2}$ pMOSFET was much lower than that in the all-Si counterpart, regardless of gate-oxide degradation by electrical stress. These results suggest that the $Si_{0.8}Ge_{0.2}$ pMOSFET is suitable for RF applications that require high speed and low 1/f noise.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.342-354
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• 2013

The aim of this work is to investigate and study the quantum effects in the modeling of nanoscale symmetric double-gate InAlAs/InGaAs/InP HEMT (High Electron Mobility Transistor). In order to do so, the carrier concentration in InGaAs channel at gate lengths ($L_g$) 100 nm and 50 nm, are modelled by a density gradient model or quantum moments model. The simulated results obtained from the quantum moments model are compared with the available experimental results to show the accuracy and also with a semi-classical model to show the need for quantum modeling. Quantum modeling shows major variation in electron concentration profiles and affects the device characteristics. The two triangular quantum wells predicted by the semi-classical model seem to vanish in the quantum model as bulk inversion takes place. The quantum effects thus become essential to incorporate in nanoscale heterostructure device modeling.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• 센서학회지
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• 제30권1호
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• pp.61-65
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• 2021

In this study, we propose a 2500 frame per second (fps) high-speed binary complementary metal oxide semiconductor (CMOS) image sensor using a gate/body-tied (GBT) p-channel metal oxide semiconductor field effect transistor-type high-speed photodetector. The GBT photodetector generates a photocurrent that is several hundred times larger than that of a conventional N+/P-substrate photodetector. By implementing an additional binary operation for the GBT photodetector with such high-sensitivity characteristics, a high-speed operation of approximately 2500 fps was confirmed through the output image. The circuit for binary operation was designed with a comparator and 1-bit memory. Therefore, the proposed binary CMOS image sensor does not require an additional analog-to-digital converter (ADC). The proposed 2500 fps high-speed operation binary CMOS image sensor was fabricated and measured using standard CMOS process.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권6호
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.