• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1870-1877
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• 1990

The electromagnetic properties of P- and n-channel split drain magnetic sensitive MOSFET fabricated using 2\ulcorner design rules and CMOS process technology has been investigated. The achieved output voltage in the double drain MOSFET was 160mV at 10\ulcorner drain current and magnetic flux density of 10kG, and the sensitivity was 1.6x10**3 V/A\ulcornerG. A further higher sensitivity was obtained by introducing a third drain in the split region. In this case, the triple drain MOSFET showed a much higher sensitivity of 2x10**3 V/A\ulcornerG under the same condition. Also, the linearity of output voltage vs. magnetic flux density was excellent.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1291-1293
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• 1998

Power MOSFETs are very important Devices in power circuit applications such as motor control, switch mode power supplies & telecommunicatioelectronics. In order to investigated the Avalanch Energy value of MOSFET due to Misalign. Some samples made under several different $P^+$ misalign and $N^+$ misalign. The relationship between evalanch energy value and misalign is investigated as well in this paper.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.692-696
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• 1997

본 연구에서는 BJT(Bipolar Junction Transistor)와 MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 등을 1MeV에너지의 전자빔을 선량을 변화시켜가며 조사시켜 그 특성 변화를 분석하였다. BJT에 대해서는 조사 전, 후의 전류 이득의 측정을 통해 base 에서의 minority-carrie의 수명 변화에 의해서 전류 이득이 감소하는 것으로 나타났으며, MOSFET의 경우는 oxide 지역의 전하량 변화에 의해서 문턱 전압이 영향을 받음을 확인할 수 있었다. BJT의 minority-carrier의 수명 감소량은 조사 선량이 증가함에 따라 직선적으로 변화함을 알 수 있었고, MOSFET의 문턱 전압의 변화는 nMOS와 pMOS의 경우 서로 다름을 관찰할 수 있었는데 이는 oxide내에서 발생하는 전하에 의해 차이가 남을 알 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.5
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• pp.818-822
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• 1987

Gate capacitances have been measured directly on small-geometry MOSFET's with the drain voltage as a parameter for various channel lengths and for p and n channel types and the characteristics have been compared with each other. The influence of 'hot carrier effect' of short channel devices on capaciatance has been compared with long channel devices. The results show that gate capacitance characteristics of short channel device deviate from those of long channel device. The accuracy of the measurement system is less than a few femto Farad, and the minimum geometry (W/L) of device for which reliable measurement can be obtained is 6/3.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.7
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• pp.584-592
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• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.

• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.964-969
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• 2014

In Super Junction MOSFET, Charge Balance is the most important issue of the trench filling Super Junction fabrication process. In order to achieve the best electrical characteristics, the N type and P type drift regions must be fully depleted when the drain bias approaches the breakdown voltage, called Charge Balance Condition. In this paper, two methods from the fabrication process were used at the Charge Balance condition: Trench angle decreasing process and Bottom implantation process. A lower on-resistance could be achieved using a lower trench angle. And a higher breakdown voltage could be achieved using the bottom implantation process. The electrical characteristics of manufactured discrete device chips are compared with those of the devices which are designed of TCAD simulation.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1977-1980
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• 1998

본 논문에서는 출력단에 동기정류기를 사용하는 영전압 스위칭 방식의 고효율 하프 브리지(H-B)컨버터에 대해 다루고자 한다. 컨버터 손실의 대부분은 출력단 정류기 부분, 주 스위치, 트랜스 등에서 발생되며, 이중 출력단 정류기에 쇼트키 다이오드를 이용하는 경우 쇼트키 다이오드의 on-drop에 의한 손실이 적지 않게 된다. 따라서 이를 감소시키기 위해 쇼트키 다이오드를 MOSFET동기 정류기로 대치하고자 한다. 동기 정류기 방식에 이용되는 MOSFET에는 도통손실이 있으나 이는 쇼트키 다이오드의 on-drop에 의한 손실에 비해 매우 작으며, 특히 MOSFET의 기생 성분을 이용하여 영전압을 구현함으로써 MOSFET의 도통 손실을 현저히 감소시킬 수 있게 된다. 또한 H-B 컨버터의 경우 주 스위치에 전원전압과 동일한 크기의 전압이 인가되므로 내압이 작은 소자의 이용이 가능하게 되며, 이와 같이 함으로써 사용 부품 수의 감소, 내압이 낮은 주 스위치의 사용, 더 나아가 효율이 높은 고효율 컨버터를 구현 할 수 있다.

• Korean Journal of Materials Research
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• v.18 no.5
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• pp.272-276
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• 2008

In submicron MOSFET devices, maintaining the ratio between the channel length (L) and the channel depth (D) at 3 : 1 or larger is known to be critical in preventing deleterious short-channel effects. In this study, n-type SOI-MOSFETs with a channel length of $0.1\;{\mu}m$ and a Si film thickness (channel depth) of $0.033\;{\mu}m$ (L : D = 3 : 1) were virtually fabricated using a TSUPREM-4 process simulator. To form functioning transistors on the very thin Si film, a protective layer of $0.08\;{\mu}m$-thick surface oxide was deposited prior to the source/drain ion implantation so as to dampen the speed of the incoming As ions. The p-type boron doping concentration of the Si film, in which the device channel is formed, was used as the key variable in the process simulation. The finished devices were electrically tested with a Medici device simulator. The result showed that, for a given channel doping concentration of $1.9{\sim}2.5\;{\times}\;10^{18}\;cm^{-3}$, the threshold voltage was $0.5{\sim}0.7\;V$, and the subthreshold swing was $70{\sim}80\;mV/dec$. These value ranges are all fairly reasonable and should form a 'magic region' in which SOI-MOSFETs run optimally.

• Journal of IKEEE
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• v.25 no.2
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• pp.350-355
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• 2021

IGBT is a power semiconductor device that contains both MOSFET and BJT structures, and it has fast switching speed of MOSFET, high breakdown voltage and high current of BJT characteristics. IGBT is a device that targets the requirements of an ideal power semiconductor device with high breakdown voltage, low V_CE-SAT, fast switching speed and high reliability. In this paper, we analyzed Gate oxide thickness, Trench Gate Width, and P+Emitter width, which are the top process parameters of 1,200V Trench Gate Field Stop IGBT, and suggested the optimized top process parameters. Using the Synopsys T-CAD Simulator, we designed IGBT devices with electrical characteristics that has breakdown voltage of 1,470 V, V_CE-SAT 2.17 V, Eon 0.361 mJ and Eoff 1.152 mJ.

• Journal of Satellite, Information and Communications
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• v.8 no.4
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• pp.124-129
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• 2013

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latch-up problem during normal operation. However, a modified NSCR_PPS device with counter pocket source(CPS) and partial p-type well(PPW) structure demonstrates highly latch-up immune current-voltage characteristics.