• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.4
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• pp.436-447
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• 2013

In this paper, Integrated circuit(IC) electromagnetic(EM) conducted immunity measurement and simulation using bulk current injection(BCI) and direct power injection(DPI) methods were conducted for 1.8 V I/O buffers. Using the equivalent circuit models developed for IC electromagnetic conducted immunity tests, we investigated the reliability of the frequency region where IC electromagnetic conducted immunity test is performed. The insertion loss for the noise injection path obtained from the simulation indicates that using only one conducted immunity test method cannot provide reliable conducted immunity test for broadband noise. Based on the forward power results, we analyzed the actual amount of EM noise injected to IC. We propose a more reliable immunity test methods for broad band noise.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.917-925
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• 2016

Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.1
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• pp.35-42
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• 2003

Differential signaling has become a popular choice for high-speed interconnection schemes on Printed Circuit Boards (PCBs), offering superior immunity to external noise. However, conventional differential transmission lines on PCBs have problems, such as crosstalk and radiated emission. To overcome these, we propose a Twisted Differential Line (TDL) structure on a multi-layer PCB. Its improved immunity to crosstalk noise and the reduced radiated emission has been successfully demonstrated by measurement. The proposed structure is proven to transmit 3 Gbps digital signals with a clear eye-pattern. Furthermore, it is subject to much less crosstalk noise and achieves a 13 dB suppression of radiated emission. Index Terms - Twisted Differential Line, Differential Signaling, Crosstalk, Radiated Emission, Transmission Line, Twisted Pair

• Journal of Semiconductor Engineering
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• v.3 no.1
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• pp.154-160
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• 2022

In this paper, we design a DC-DC boost converter with RF noise immunity to supply a stable positive output voltage for OLED displays. For RF noise immunity, an input voltage variation reduction circuit (IVVRC) is adopted to ensure display quality by reducing the undershoot and overshoot of output voltage. The boost converter for a positive voltage Vpos operates in the SPWM-PWM dual mode and has a dead-time controller using a dead-time detector, resulting in increased power efficiency. A chip was fabricated using a 0.18 um BCDMOS process. Measurement results show that power efficiency is 30% ~ 76% for load current range from 1 mA to 100 mA. The boost converter with the IVVRC has an overshoot of 6 mV and undershoot of 4 mV compared to a boost converter without that circuit with 18 mV and 20 mV, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.202-211
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• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.482-482
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• 2000

The essential requirements of neural network for human skill transfer are fast convergence, high storage capacity, and strong noise immunity. Bidirectional associative memory(BAM) suffering from low storage capacity and abundance of spurious memories is rarely used for skill transfer application though it has fast and wide association characteristics for visual data. This paper suggests generalization of classical BAM structure and new learning algorithm which uses supervised learning to guarantee perfect recall starting with correlation matrix. The generalization is validated to accelerate convergence speed, to increase storage capacity, to lessen spurious memories, to enhance noise immunity, and to enable multiple association using simulation work.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1643-1647
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• 2003

This paper, we propose a new high noise immunity phase-locked loop(PLL) which can suppress the high incident noise coupling with large amplitude and long period to the input frequency of PLL and keeps constant frequency and phase of the VCO output for providing the high stability distribution clock pulse.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.1
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• pp.196-200
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• 2015

The switching noise in the power electronics of the power conversion equipment (Power Conditioning System) for large energy storage devices are generated. Since the burst-level transient noise from being generated in the power system at a higher power change process influences the control circuit of the low voltage driver circuit. Noise may cause the malfunction of the control device even if no dielectric breakdown leads to a control circuit. To overcome this, this paper proposes the installation of an additional nano-surge protection device on the power supply DC output circuit of the battery management unit.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.