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A Flipflop with Improved Noise Immunity  

Kim, Ah-Reum (School of Electrical Engineering and Computer Science, Seoul National University)
Kim, Sun-Kwon (School of Electrical Engineering and Computer Science, Seoul National University)
Lee, Hyun-Joong (School of Electrical Engineering and Computer Science, Seoul National University)
Kim, Su-Hwan (School of Electrical Engineering and Computer Science, Seoul National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.8, 2011 , pp. 10-17 More about this Journal
Abstract
As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.
Keywords
flipflop; noise immunity; setup time; hold time; power;
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