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http://dx.doi.org/10.5515/KJKIEES.2016.27.10.917

DTMOS Schmitt Trigger Logic Performance Validation Using Standard CMOS Process for EM Immunity Enhancement  

Park, SangHyeok (College of Information and Communication Engineering, Sunkyunkwan University)
Kim, SoYoung (College of Information and Communication Engineering, Sunkyunkwan University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.27, no.10, 2016 , pp. 917-925 More about this Journal
Abstract
Schmitt Trigger logic is a gate level design method to have hysteresis characteristics to improve noise immunity in digital circuits. Dynamic Threshold voltage MOS(DTMOS) Schmitt trigger circuits can improve noise immunity without adding additional transistors but by controlling substrate bias. The performance of DTMOS Schmitt trigger logic has not been verified yet in standard CMOS process through measurement. In this paper, DTMOS Schmitt trigger logic was implemented and verified using Magna $0.18{\mu}m$ MPW process. DTMOS Schmitt trigger buffer, inverter, NAND, NOR and simple digital logic circuits were made for our verification. Hysteresis characteristics, power consumption, and delay were measured and compared with common CMOS logic gates. EM Immunity enhancement was verified through Direct Power Injection(DPI) noise immunity test method. DTMOS Schmitt trigger logics fabricated using CMOS process showed a significantly improved EM Immunity in 10 M~1 GHz frequency range.
Keywords
CMOS; DTMOS Schmitt Trigger; Hysteresis Characteristic; Noise Immunity; Low Power;
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