• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Anxiety and mood
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• v.8 no.1
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• pp.3-8
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• 2012

Patients with panic disoder (PD) show recollection of their first panic attack, which resembles a trauma that is perceived as an unexpected frightening and subjectively life-threatening event. Information-processing models suggest that anxiety disorders may be characterized by a memory bias for threat-related information. This paper reviews the previous researches that investigated the implicit and/or explicit biases in patients with panic disorder. Among the 17 studies, which addressed the explicit memory bias in PD patients, 11 (64.7%) were found to be explicit memory bias in PD patients. In regards to the implicit memory bias, 4 out of 9 studies (44.4%) were found to support the memory bias. The result shows that evidence of explicit memory bias in PD patients was supported by a number of previous researches. However, evidence of implicit memory bias seems less robust, thus, needs further research for replication. Also, development of new paradigms and applications of various methods will be needed in further researches on memory bias in PD patients.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.43.5-43
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• 2001

This paper considers a new synthesis of the optimally performing brain-state-in-a-box (BSB) neural associative memory given a set of prototype patterns to be stored as asymptotically stable equilibrium points with the large and uniform size of the domain of attraction (DOA). First, we propose a new theorem that will be used to provide a guideline in design of the BSB neural associative memory. Finally, a design example is given to illustrate the proposed approach and to compare with existing synthesis methods.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.245-248
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• 1998

Until now, to solve the problem, the lack of memory at TDX-10A ESS (Electronic Switching System), we have extended only main memory of the systems. However, this method is useful for only Transitcall Processing Subsystems and, it is not an effective way that is able to apply to all Subsystems of ESS because of the financial aspect. In this paper, we will introduce a new method which uses Non-Resident Program. This method utilizes main memory more effectively. We will also analyze the effectiveness resulting from test of new method applied to TDX-10A ESS.

• Proceedings of the KSME Conference
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• 2007.05a
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• pp.957-962
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• 2007

This paper describes a new mechanism for improving the force of actuators based on shape memory alloys (SMA) by increasing the number at which a coil pattern SMA spring can evenly be heated. This structure accomplishes a high efficient transformation between force and displacement overcoming the main mechanical drawback of shape memory alloys, that being the limit strain. A pantograph manipulator actuated by the introduced new mechanism has been designed for this research. Mechanical structure and driving mechanism of this manipulator are described in detail, and its control algorithm and current amplifier circuit in a position control system are designed.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.488-493
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• 1989

In this paper, the structure of CMAC address mapping is first revisited, and the address hashing function and the random mapping is discussed in the conventional CMAC implementation. Then the effective size of CMAC memory is derived from the modulus property of the CMAC address vector, and a new hashing function for the effective memory mapping is proposed for a CMAC implementation with feasible memory size and no troublesome random mapping. Finally, the performance of the conventional CMAC learning algorithm and that of the proposed new CMAC scheme arc compared via simulations.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.234-237
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• 1996

The amorphous chalogenide semiconductors are new material in semiconductor physics. Their properties, especially electronic and optical properties are main motives for device application. Amorphous As$_{10}$Ge$_{15}$ Te$_{75}$material has the stable ac conductivity at high frequency and the dc memory switching property. At higher frequency than 10MHz, ac conductivity of As$_{10}$Ge$_{15}$ Te$_{75}$ thin film is much higher than below frequency and independent of temperature and frequency. If the dc voltages are applied between edges of thin film, one can see the dc memory switching phenomenon, in other words the dc conductivity increases quite a few of magnitude after the threshold voltage is applied. Using the stable ac conductivity at high frequency and the increase of conductivity after dc memory switching, As$_{10}$Ge$_{15}$ Te$_{75}$thin film is considered as new material for microwave switch devices.vices.es.vices.

• Journal of Information Technology Applications and Management
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• v.13 no.2
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• pp.115-126
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• International Journal of Internet, Broadcasting and Communication
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• v.11 no.1
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• pp.69-74
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• 2019

The compiler is the key of the prototyping framework for the new memory system. These compiler-centric prototyping tools have several components, including compiler, linker, assembler, and standard libraries. It takes a lot of cost and man power to develop it all at zero base. Therefore, developer usually use a development framework to develop these prototyping tools efficiently. These development frameworks should be free of licensing issues when considering the commercialization of development results. Thus, developer should investigate the development framework, which is free from licensing issues and that provides all of the development environment to enable actual execution. There are three representative compiler-centric development frameworks: GCC, Clang (LLVM), and MS visual studio. There are some differences depending on the release version among them. And, there are some limitations to the freeware and commercial use. We chose LLVM here to explain the development of prototyping tools. This information will help accelerate the development of prototyping tools and will help reduce system development costs.