JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

  • Kim, Yoon (Flash Design Team, Memory Division, Samsung Electronics Company, Ltd.) ;
  • Seo, Joo Yun (ISRC and the Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Lee, Sang-Ho (ISRC and the Department of Electrical Engineering and Computer Science, Seoul National University) ;
  • Park, Byung-Gook (ISRC and the Department of Electrical Engineering and Computer Science, Seoul National University)
  • Received : 2014.05.12
  • Accepted : 2014.08.23
  • Published : 2014.10.30
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Abstract

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

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References

  1. J. Jang, et al, "Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," in VLSI Symp. Tech. Dig., pp. 192-193, month 2008.
  2. Y. Kim, et al, "Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline STacked ARray," IEEE Trans. Electron Devices, vol. 59, no. 1, pp. 35-45, Jan. 2012. https://doi.org/10.1109/TED.2011.2170841
  3. W. Kim, et al, "Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)," in IEDM Tech. Dig., 2013, pp. 3.8.1-3.8.4.
  4. Y. Kim, M. Kang, S. H. Park, and B.-G. Park, "Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array," IEEE Electron Device Lett., vol. 34, no. 8, pp. 990-992, July. 2013. https://doi.org/10.1109/LED.2013.2262174
  5. K.-D. Suh, et al, "A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme," in ISSCC Dig. Tech., pp. 128-129, Feb. 1995.

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