[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2014.14.5.566

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Kim, Yoon (Flash Design Team, Memory Division, Samsung Electronics Company, Ltd.)
Seo, Joo Yun (ISRC and the Department of Electrical Engineering and Computer Science, Seoul National University)
Lee, Sang-Ho (ISRC and the Department of Electrical Engineering and Computer Science, Seoul National University)
Park, Byung-Gook (ISRC and the Department of Electrical Engineering and Computer Science, Seoul National University)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.14, no.5, 2014 , pp. 566-571 More about this Journal

Abstract

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.

Keywords

3D NAND flash; ISPP; stacked array(STAR); SONOS nanowire; elliptical nanowire;

Citations & Related Records

Reference

1	J. Jang, et al, "Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory," in VLSI Symp. Tech. Dig., pp. 192-193, month 2008.
2	K.-D. Suh, et al, "A 3.3 V 32 Mb NAND Flash memory with incremental step pulse programming scheme," in ISSCC Dig. Tech., pp. 128-129, Feb. 1995.
3	Y. Kim, et al, "Three-Dimensional NAND Flash Architecture Design Based on Single-Crystalline STacked ARray," IEEE Trans. Electron Devices, vol. 59, no. 1, pp. 35-45, Jan. 2012. DOI
4	W. Kim, et al, "Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)," in IEDM Tech. Dig., 2013, pp. 3.8.1-3.8.4.
5	Y. Kim, M. Kang, S. H. Park, and B.-G. Park, "Three-Dimensional NAND Flash Memory Based on Single-Crystalline Channel Stacked Array," IEEE Electron Device Lett., vol. 34, no. 8, pp. 990-992, July. 2013. DOI ScienceOn

Reference

6	Yoon Kim. (2015) Japanese Journal of Applied Physics Gated twin-bit silicon–oxide–nitride–oxide–silicon NAND flash memory for high-density nonvolatile memory / 54 (6) , 064201
2	Sungjun Kim. (2016) JSTS:Journal of Semiconductor Technology and Science Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device / 16 (2) , 147
12	Yoon Kim. (2016) IEEE Electron Device Letters Down-Coupling Phenomenon of Floating Channel in 3D NAND Flash Memory / 37 (12) , 1566
7	Sang-Ho Lee. (2016) IEEE Electron Device Letters Layer Selection by Multi-Level Permutation in 3-D Stacked NAND Flash Memory / 37 (7) , 866
1	Seunghyun Kim. (2016) Japanese Journal of Applied Physics Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory / 56 (1) , 014302
5	Sungjun KIM. (2016) IEICE Transactions on Electronics Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell / E99.C (5) , 547
4	(2017) IEEE Transactions on Device and Materials Reliability Investigation of Retention Characteristics for Trap-Assisted Tunneling Mechanism in Sub 20-nm NAND Flash Memory / 17 (4) , 758
9	(2017) IEEE Electron Device Letters Natural Local Self-Boosting Effect in 3D NAND Flash Memory / 38 (9) , 1236
6	Sungjun Kim. (2015) Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena -based resistive random-access memory with MIS structure / 33 (6) , 062201
12	Kyunghwan Lee. (2015) Semiconductor Science and Technology Modeling of apparent activation energy and lifetime estimation in NAND flash memory / 30 (12) , 125006
2	Sungjun Kim. (2016) Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena -based resistive random-access memory cell with Ti buffer layer / 34 (2) , 022204
1	(2018) IEEE Transactions on Electron Devices 3-D Floating-Gate Synapse Array With Spike-Time-Dependent Plasticity / 65 (1) , 101
21	Sungjun Kim. (2016) Applied Physics Letters /TiN structures / 108 (21) , 212103
21	Sungjun Kim. (2015) Applied Physics Letters -based resistive-switching random-access memory cell with tunnel barrier for high density integration and low-power applications / 106 (21) , 212106