• Journal of Power Electronics
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• 제5권4호
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• pp.247-256
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• 2005

In order to harvest power in an efficient manner from a micro piezoelectric (PZT) device for charging the battery of a remote system, a new AC/DC resonant pulse power converter is proposed. The proposed power converter has two stages in the power conversion process. The first stage includes N-type MOSFET full bridge rectifier. The second stage includes a boost converter having an N-type MOSFET and a P-type MOSFET. MOSFETs work in the $1^{st}$ or $3^{rd}$ quadrant region. A small inductor for the boost converter is assigned in order to make the size of the power converter as small as possible, which makes the on-interval of the MOSFET switch of the boost converter ultimately short. Due to this short on-interval, the parasitic junction capacitances of MOSFETs affect the performance of the power converter system. In this paper, the performance of the new converter is analytically and experimentally evaluated with consideration of the parasitic capacitance of switching devices.

• 한국정보통신학회논문지
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• 제3권2호
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• pp.471-475
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• 1999

$N{_2}O$ 게이트 산화막을 사용한 nMOSFET가 금속 플라즈마 식각 피해에 대한 면역도가 동일한 두께의 순수한 산화막을 갖는 nMOSFET보다 향상됨을 보여준다. Area Antenna Ratio(AAR)를 증가시킴에 따라 $N{_2}O$ 산화막을 갖는 nMOSFET는 좁은 초기 분포 특성과 정전계 스트레스하에서 더 작은 열화특성을 보이는 데 이는 Si기판과 산화막 계면에서의 질소기의 영향으로 설명되어진다. 또한 $N{_2}O$ 게이트 산화막을 사용하면 순수한 게이트 산화막을 사용할 때 보다 금속 Area Antenna Ratio(AAR)과 Perimeter Area ratio(PAR) 의 최대 허용 크기를 더 증가할 수 있다. 이러한 $N{_2}O$ 게이트 산화막을 갖는 NMOSFET의 개선은 Si기판과 $N{_2}O$ 산화막 계면에 있는 질소기에 의한 계면 강도의 영향 때문으로 판단된다.

• 한국정보통신학회논문지
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• 제6권1호
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• pp.109-114
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• 2002

본 논문에서는 나노규모의 채널길이를 가지는 Si-기반 MOSFET의 문턱전압은 시뮬레이션하여 그 결과를 나타내었다. 180nm의 게이트 길이를 가지는 소자를 기본소자로 하여 정전압 스켈링과 평면 스켈링을 적용하여 소자를 축소하고 시뮬레이션 하였다. 이러한 MOSFET은 LDD(lightly doped drain)구조를 가지고 있으며, 이 구조는 드레인 영역에서의 전계의 크기와 단채널 효과를 줄여준다. 이 영역에서의 고전계현상은 축소에 기인한다. 이러한 소자들의 문턱전압을 조사하고 분석하였다. 이러한 분석은 IC의 응용한계 및 VLSI의 기본자료로 사용될 수 있을 것이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.735-736
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• 1998

Reduction of hot carrier degradation in MOS devices has been one of the most serious concerns for MOS-ULSIs. In this paper, three types of LDD structure for suppression of hot carrier degradation, such as spacer-induced degradation and decrease of performance due to increase of series resistance will be investigated. LDD-nMOSFETs used in this study had three different drain structure. (1) conventional ${\underline{S}}urface$ type ${\underline{L}}DD$(SL), (2) ${\underline{B}}uried$ type ${\underline{L}}DD$(BL), (3) ${\underline{S}}urface$urface ${\underline{I}}mplantation$ type LDD(SI). As a result, the surface implantation type LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structure.

• 한국전기전자재료학회논문지
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• 제24권4호
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• pp.271-275
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• 2011

In this paper, thermal stability of palladium germanide (Pd germanide) is analyzed for high performance Schottky barrier germanium metal oxide semiconductor field effect transistors (SB Ge-MOSFETs). Pd germanide Schottky barrier diodes were fabricated on n-type Ge-on-Si substrates and the formed Pd germanide shows thermal immunity up to $450^{\circ}C$. The barrier height of Pd germanide is also characterized using two methods. It is shown that Pd germanide contact has electron Schottky barrier height of 0.569~0.631 eV and work function of 4.699~4.761 eV, respectively. Pd germanide is promising for the nanoscale Schottky barrier Ge channel MOSFETs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.861-864
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• 2005

Performing accurate and repeatable low frequency noise measurement is critical for modeling and simulation of flicker noise. Through the accurate and repeatable on-wafer measurement, low frequency noise characteristics of the 0.18 ${\mu}m$ n-MOSFETs are discussed. And on-wafer flicker noise measurement system is presented. The on-wafer measurement system consists of cascade probe station, low noise current amplifier (SR570), and dynamic signal analyzer (HP35670A).

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권1호
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• pp.17-22
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• 2001

The floating-gate MOSFETs were fabricated by employing 1.5 m n-well CMOS process and their optical-electrical properties were characterized for the application to CMOS image sensor system. Based on the simulation of energy band diagram and operating mechanism of parasitic BJT were proposed as solutions for the increase of photo-current value. In order to realize them, MOSFETs having multi-gate and channel structures were fabricated and 60% increase in photo-current was achieved through enlargement of depletion layer and parallel connection of parasitic BJTs by channel division.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 추계학술대회 논문집 학회본부 C
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• pp.956-958
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• 1999

We designed and fabricated p-type MOSFETs with floating gate in n-type well lesion and examined their photo characteristics. The fabricated MOBFETs showed a high photo-respsonse characteristics, indicating a possibility as a photo sensor. The structures of MOSFETs were changed as to the number of gate and channel. As the number of channel increased, the induced current by light source s increased. However, the effect of the number of gate was negligble on the photo-response characteristics of the device.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• 한국전기전자재료학회논문지
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• 제16권7호
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• pp.584-592
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• 2003

6H-SiC MOSFETs and digital ICs have been fabricated and characterized. PMOS devices are fabricated on an n-type epilayer while the NMOS devices are fabricated on implanted p-wells. NMOS and PMOS devices use a thermally grown gate oxide. SiC MOSFETs are fabricated using different impurity activation methods such as high temperature and newly proposed laser annealing methods. Several digital circuits, such as resistive road NMOS inverters, CMOS inverters, resistive road NMOS NANDs and NORs are fabricated and characterized.