• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• 센서학회지
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• 제27권3호
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• pp.150-155
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• 2018

Three different structures of GaN MOSFETs with trap distributions, trap levels, and densities were simulated, and its results were analyzed. Two of them are Schottky barrier MOSFETs(SB-MOSFETs): one with a p-type GaN body while the other is in the accumulation mode MOSFET with an undoped GaN body and regrown source/drain. The trap levels, distributions and densities were considered based on the measured or calculated properties. For the SB-MOSFET, the interface trap distribution affected the threshold voltage significantly, but had a relatively small influence on the subthreshold swing, while the bulk trap distribution affects the subthreshold swing more.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• 대한전자공학회논문지
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• 제26권9호
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• pp.1375-1380
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• 1989

Mobility reduction parameters are extracted using a method based on the exploitatiion of Id-Vg and Gm-Vg characteristics of short channel n-MOSFETs in strong inversion region at room temperature. It is found that the reduction of the maximum field effect mobility, \ulcornerFE,max, with the channel length is due to i) the difference between the threshold voltage and the gate voltage which corresponds to the maximum transconductance, and ii) the channel length dependence of the mobility attenuation coefficient, \ulcorner The low field mobility, \ulcorner, is found to be independent of the channel length down to 0.25 \ulcorner ofeffective channel length. Also, the channel length reduction, -I, the mobility attenuation coefficient, \ulcorner the threshold voltage, Vt, and the source-drain resistance, Rsd, are determined from the Id-Vg and -gm-Vg characteristics n-MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권1호
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• pp.41-47
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• 2015

In this paper, the effective electron Schottky barrier height (${\Phi}_{Bn}$) of the Ni silicide/n-silicon (100) interface was studied in accordance with different thicknesses of the antimony (Sb) interlayer for high performance n-channel MOSFETs. The Sb interlayers, varying its thickness from 2 nm to 10 nm, were deposited by radio frequency (RF) sputtering on lightly doped n-type Si (100), followed by the in situ deposition of Ni/TiN (15/10 nm). It is found that the sample with a thicker Sb interlayer shows stronger ohmic characteristics than the control sample without the Sb interlayer. These results show that the effective ${\Phi}_{Bn}$ is considerably lowered by the influence of the Sb interlayer. However, the current level difference between Schottky diodes fabricated with Sb/Ni/TiN (8/15/10 nm) and Sb/Ni/TiN (10/15/10 nm) structures is almost same. Therefore, considering the process time and cost, it can be said that the optimal thickness of the Sb interlayer is 8 nm. The effective ${\Phi}_{Bn}$ of 0.076 eV was achieved for the Schottky diode with Sb/Ni/TiN (8/15/10 nm) structure. Therefore, this technology is suitable for high performance n-channel MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.69-76
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• 2005

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

• ETRI Journal
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• 제27권4호
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• pp.439-445
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• 2005

We introduce a strained-SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si-cap layers in n-channel and p-channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high-electron-mobility Si surface channel in nMOSFETs and a compressively strained high-hole-mobility $Si_{0.8}Ge_{0.2}$ buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate-leakage levels. Unlike the conventional strained-Si CMOS employing a relatively thick (typically > 2 ${\mu}m$) $Si_xGe_{1-x}$ relaxed buffer layer, the strained-SiGe CMOS with a very thin (20 nm) $Si_{0.8}Ge_{0.2}$ layer in this study showed a negligible self-heating problem. Consequently, the proposed strained-SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• 한국정보전자통신기술학회논문지
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• 제16권4호
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• pp.180-186
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• 2023

본 논문은 4세대 VNAND 공정으로 만들어진 고전압 SiO2 절연층 nMOSFET의 n⁺ 및 p⁺ poly-Si 게이트에서의 positive bias temperature instability(PBTI) 열화에 대해 비교하고 각각의 메커니즘에 대해 분석한다. 게이트 전극 물질의 차이로 인한 절연층의 전계 차이 때문에 n⁺/nMOSFET의 열화가 p⁺/nMOSFET의 열화보다 더 클 것이라는 예상과 다르게 오히려 p⁺/nMOSFET의 열화가 더 크게 측정되었다. 원인을 분석하기 위해 각각의 경우에 대해 interface state와 oxide charge를 각각 추출하였고, 캐리어 분리 기법으로 전하의 주입과 포획 메커니즘을 분석하였다. 그 결과, p⁺ poly-Si 게이트에 의한 정공 주입 및 포획이 p⁺/nMOSFET의 열화를 가속시킴을 확인하였다.