JSTS:Journal of Semiconductor Technology and Science

  • 제5권2호
  • /
  • Pages.69-76
  • /
  • 2005
  • /
  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Characteristics of Schottky Diode and Schottky Barrier Metal-Oxide-Semiconductor Field-Effect Transistors

  • Jang, Moon-Gyu (Nano-electronic Device Team, Future Technology Research Division, Electronics and Telecommunications Research Institute) ;
  • Kim, Yark-Yeon (Nano-electronic Device Team, Future Technology Research Division, Electronics and Telecommunications Research Institute) ;
  • Jun, Myung-Sim (Nano-electronic Device Team, Future Technology Research Division, Electronics and Telecommunications Research Institute) ;
  • Lee, Seong-Jae (Nano-electronic Device Team, Future Technology Research Division, Electronics and Telecommunications Research Institute)
  • 발행 : 2005.06.30
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are evaluated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are determined as $1.5{\times}10^{13} traps/cm^2$, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by $N_2$ annealing. Based on the diode characteristics, various sizes of erbium- silicided/platinum-silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from 20 m to 35nm. The manufactured SB-MOSFETs show excellent drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are compatible with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

키워드

참고문헌

  1. S. Zhu, J. Chen, M.-F. Li, S. J. Lee, J. Singh, C. X. Zhu, A. Du, C. H. Tung, A. Chin and D. L. Kwong, N-type Schottky barrier source/drain MOSFET using ytterbium silicide, IEEE Electron Device Lett., vol. 25, pp. 565-567, August. 2004 https://doi.org/10.1109/LED.2004.831582
  2. M. Jang, Y. Kim, J. Shin, S. Lee, and K. Park, 'A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor fielde-ffect transistor', Appl. Phys. Lett., vol. 84, pp. 741-743, Feb. 2004 https://doi.org/10.1063/1.1645665
  3. J. Kedzierski, P. Xuan, Erik H. Anderson, J. Bokor, T. J. King, and C. Hu, 'Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime', Tech. Dig. . Int. Electron Devices Meet. 2000, 57 (2000) https://doi.org/10.1109/IEDM.2000.904258
  4. R.T.Tung, Phys. Rev., B45, 13509 (1992) https://doi.org/10.1103/PhysRevB.45.13509
  5. R.B. Darling, Current-voltage characteristics of Schottky barrier diodes with dynamic interfacial defect state occupancy , IEEE Trans. Electron. Devices, vol. 43, pp. 1153-1160, July, 1996 https://doi.org/10.1109/16.502427
  6. S.M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1981, pp. 379-390
  7. H. D. Lee, Characterization of shallow silicided junctions for sub-quarter micron ULSI technology-extraction of silicidation induced Schottky contact area, , IEEE Trans. Electron Devices, vol. 47, pp. 762-767, Apr. 2000 https://doi.org/10.1109/16.830991
  8. V. Sonnenberg, and J. A. Martino, Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction, Solid-State Electronics, vol. 43, pp. 2191-2199, 1999 https://doi.org/10.1016/S0038-1101(99)00191-4
  9. S. Vandre, T. Kalka, C. Preinesberger, and M. Dahne-Prietsch, Flatband conditions observed for lanthanidesilicide monolayers on n-type Si(111) , Physical Review Letters, vol. 82, pp. 1927-1930, March, 1999 https://doi.org/10.1103/PhysRevLett.82.1927
  10. A. Kinoshita, K. Uchida, and J. Koga, Experimental evidence of gate-induced Schottky barrier height lowering due to image force in gated Schottky diodes , Solid State Devices and Materials, 2003, pp. 710-711
  11. M. Jang, K. Kang, S. Lee, and K. Park, 'Simulation of Schottky barrier tunnel transistor using simple boundary condition', Appl. Phys. Lett., vol. 82, pp. 2718-2720, April. 2003 https://doi.org/10.1063/1.1569415
  12. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie and Y. Arimoto, Scaling theory for double-gate SOI MOSFET s , IEEE Trans. Elect. Dev. Vol. 40, pp. 2326, 1993 https://doi.org/10.1109/16.249482