• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.146-152
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• 2014

The temperature dependence of strain-enhanced electron mobility in nMOSFETs is investigated by using a self-consistent Schr$\ddot{o}$dinger-Poisson solver. The calculated results suggest that vertical compressive stress is more efficient to maintain the strain-enhanced electron mobility than longitudinal tensile stress in high temperature condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.277-282
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• 2017

Nickel germanide (NiGe) is one of the most promising alloy materials for source/drain (S/D) of Ge MOSFETs. However, NiGe has limited thermal stability up to $450^{\circ}C$ which is a challenge for fabrication of Ge MOSFETs. In this paper, a novel method is proposed to improve the thermal stability of NiGe using Co interlayer. As a result, we found that the thermal stability of NiGe was improved from $450^{\circ}C$ to $570^{\circ}C$ by using the proposed Co interlayer. Furthermore, we found that current-voltage (I-V) characteristic was improved a little by using Co/Ni/TiN structure after post-annealing. Therefore, NiGe formed by the proposed Co interlayer that is, Co/Ni/TiN structure, is a promising technology for S/D contact of Ge MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.10-15
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• 2006

Various sizes of erbium/platinum silicided n/p-type Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are manufactured from $20{\mu}m$ to 10nm. The manufactured SB-MOSFETs show excellent DIBL and subthreshold swing characteristics due to the existence of Schottky barrier between source and channel. It is found that the minimization of trap density between silicide and silicon interface and the reduction of the underlap resistance are the key factors for the improvement of short channel characteristics. The manufactured 10 nm n-type SBMOSFET showed $550{\mu}A/um$ saturation current at $V_{GS}-V_T$ = $V_{DS}$ = 2V condition ($T_{ox}$ = 5nm) with excellent short channel characteristics, which is the highest current level compared with reported data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.94-99
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• 2004

silicided 50-nm-gate-length n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs) with 5 nm gate oxide thickness are manufactured. The saturation current is $120{\mu}A/{\mu}m$ and on/off-current ratio is higher than $10^5$ with low leakage current less than $10{\mu}A/{\mu}m$. Novel phenomena of this device are discussed. The increase of tunneling current with the increase of drain voltage is explained using drain induced Schottky barrier thickness thinning effect. The abnormal increase of drain current with the decrease of gate voltage is explained by hole carrier injection from drain into channel. The mechanism of threshold voltage increase in SB-MOSFETs is discussed. Based on the extracted model parameters, the performance of 10-nm-gate-length SB-MOSFETs is predicted. The results show that the subthreshold swing value can be lower than 60 mV/decade.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.7
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• pp.559-563
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• 2002

A threshold voltage model of SiC N-channel MOSFETs for high-temperature and hard radiation environments has been developed and verified by comparing with experimental results. The proposed model includes the difference in the work functions, the surface potential, depletion charges and SiC/$SiO_2$acceptor-like interface state charges as a function of temperature. Simulations of the model shoved that interface slates were the most dominant factor for the threshold voltage decrease as the temperature increase. To verify the model, SiC N-chnnel MOSFETS were fabricated and threshold voltages as a function of temperature were measured and compared wish model simulations. From these comparisons, extracted density of interface slates was $4{\times}10^{12}\textrm{cm}^{-2}eV^{-1}$.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.150-151
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• 2006

$Si_{0.88}Ge_{0.12}$/Si heterostructure channels grown by RPCVD were employed to n-type metal oxide semiconductor field effect transistors(MOSFETs), and their electrical properties were investigated. SiGe nMOSFETs presented very high transconductance compared to conventional Si-bulk MOSFETs, regardless substantial drawbacks remaining in subthreshold-slope, $I_{off}$, and leakage current level. It looks worthwhile to utilize excellent transconductance properties into rf applications requesting high speed and amplification capability, although optimization works on both device structure and unit processes are necessary for enhanced isolation and reduced power dissipation.

• Transactions on Electrical and Electronic Materials
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• v.14 no.6
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• pp.291-294
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• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.92-97
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• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.12
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• pp.2258-2263
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• 2006

In this parer, hump characteristics of short-channel nMOSFETs induced by moistures of the ILD(inter-layer dielectric) layer in the shallow trench isolation (STI) process are investigated and the method for hump suppression is proposed Using nMOSFETs with various types of the gate and a measurement of TDS-APIMS (Thermal Desorption System-Atmospheric Pressure ionization Mass Spectrometry), hump characteristics were systematically analyzed and the systemic analysis based hump model was presented; the ILD layer over poly-Si gate of nMOSFET generates moistures, but they can't diffuse out of the SiN layer due to the upper SiN layer. Consequently, they diffuses into the edge between the gate and STI and induces short-channel hump. In order to eliminate moisture in the ILD layer by out-gassing method, the annealing process prior to the deposition of the SiN layer was carried out. As the result, short-channel humps of the nMOSFETs were successfully suppressed.