Transactions on Electrical and Electronic Materials

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Some Device Design Considerations to Enhance the Performance of DG-MOSFETs

  • Mohapatra, S.K. (Department of Electrical Engineering, National Institute of Technology) ;
  • Pradhan, K.P. (Department of Electrical Engineering, National Institute of Technology) ;
  • Sahu, P.K. (Department of Electrical Engineering, National Institute of Technology)
  • Received : 2012.10.19
  • Accepted : 2013.10.24
  • Published : 2013.12.25
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Abstract

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

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References

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