• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.117-118
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• 2008

High-pressure deuterium annealing process is proposed and investigated for enhanced electrical and reliability properties of 512Mb DDR2 DRAM without increase in process complexity. High pressure deuterium annealing (HPDA) introduced during post metal anneal (PMA) improves not only DRAM performance but also reliability characteristics of MOSFET. Compared with a control sample annealed in a conventional forming gas, additional annealing in a high pressure deuterium ambient at $400^{\circ}C$ for 30 min decreased G1DL current and junction leakage. The improvements can be explained by deuterium incorporation at $SiO_2$/Si substrate interface near isolation trench edge.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.1-7
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• 2013

In this paper, a biosensor based on a gated lateral bipolar junction transistor (BJT) is proposed. The gated lateral BJT can function as both a metal-oxide-semiconductor field-effect transistor (MOSFET) and a BJT. By using the self-assembled monolayer (SAM) method, the C-reactive protein antibodies were immobilized on the floating gate of the device as the sensing membrane. Through the experiments, the characteristics of the biosensor were analyzed in this study. According to the results, it is indicated that the gated lateral BJT device can be successfully applied as a biosensor. Additionally, we found that the sensitivity of the gated lateral BJT can be varied by adjusting the emitter (source) bias.

• 반도체디스플레이기술학회지
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• 제10권1호
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• pp.27-32
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• 2011

In this study, we have investigated the power conversion efficiency of organic solar cells utilizing conjugated polymer/fullerene bulk-hetero junction(BHJ) device structures. We have fabricated poly(3-hexylthiophene)(P3HT), poly[2methoxy-5-(3',7'-dimethyloctyl-oxy)-1-4-phenylenevinylene] as an electron donor, [6,6]-phenyl $C_{61}$ butyric acid methylester(PCBM-$C_{61}$)as an electron acceptor, and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate)(PEDOT:PSS) used as a hole injection layer(HIL), after fabricated active layer, between active layer and metal cathode(Al) deposited LiF interlayer(5 nm). The properties of fabricated organic solar cell(OSC) devices have been analyzed as a function of different thickness. The electrical characteristics of the fabricated devices were investigated by means J-V, fill factor(FF) and power conversion efficiency(PCE). We observed the highest PCEs of 0.628%(MDMO-PPV:PCBM-$C_{61}$) and 2.3%(P3HT:PCBM-$C_{61}$) with LiF inter-layer at the highest thick active layer, which is 1.3times better than the device without LiF inter-layer.

• 마이크로전자및패키징학회지
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• 제25권4호
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• pp.9-15
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• 2018

This paper shows the principles and characteristics of the transient liquid phase (TLP) bonding technology for power modules packaging. The power module is semiconductor parts that change and manage power entering electronic devices, and demand is increasing due to the advent of the fourth industrial revolution. Higher operation temperatures and increasing current density are important for the performance of power modules. Conventional power modules using Si chip have reached the limit of theoretical performance development. In addition, their efficiency is reduced at high temperature because of the low properties of Si. Therefore, Si is changed to silicon carbide (SiC) and gallium nitride (GaN). Various methods of bonding have been studied, like Ag sintering and Sn-Au solder, to keep up with the development of chips, one of which is TLP bonding. TLP bonding has the advantages in price and junction temperature over other technologies. In this paper, TLP bonding using various materials and methods is introduced. In addition, new TLP technologies that are combined with other technologies such as metal powder mixing and ultrasonic technology are also reviewed.

• 한국전기전자재료학회논문지
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• 제16권9호
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.97-98
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• 2006

High current behaviors of extended drain n-type metal-oxide-semiconductor field effects transistor (EDNMOS) with double polarity source (DPS) for electrostatic discharge (ESD) protection are analyzed. Simulation based contour analyses reveal that combination of bipolar junction transistor operation and deep electron channeling induced by high electron injection gives rise to the second on-state. Therefore, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• ETRI Journal
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• 제27권4호
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• pp.449-452
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• 2005

The electrical characteristics of solid state devices such as the bipolar junction transistor (BJT), metal-oxide semiconductor field-effect transistor (MOSFET), and other active devices are altered by impinging photon radiation and temperature in the space environment. In this paper, the threshold voltage, the breakdown voltage, and the on-resistance for two kinds of MOSFETs (200 V and 100 V of $V_{DSS}$) are tested for ${\gamma}-irradiation$ and compared with the electrical specifications under the pre- and post-irradiation low dose rates of 4.97 and 9.55 rad/s as well as at a maximum total dose of 30 krad. In our experiment, the ${\gamma}-radiation$ facility using a low dose, available at Korea Atomic Energy Research Institute (KAERI), has been applied on two commercially available International Rectifier (IR) products, IRFP250 and IRF540.

• Journal of the Optical Society of Korea
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• 제15권1호
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• pp.1-3
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• 2011

We characterize and analyze silicon avalanche photodetectors (APDs) fabricated with standard complementary metal-oxide-semiconductor (CMOS) technology. Current characteristics, responsivity, avalanche gain, and photodetection bandwidth of CMOS-APDs based on two types of PN junctions, N-well/P-substrate and $P^+$/N-well junctions, are compared and analyzed. It is demonstrated that the CMOS-APD using the $P^+$/N-well junction has higher responsivity as well as higher photodetection bandwidth than N-well/P-substrate. In addition, the important factors influencing CMOS-APD performance are clarified from this investigation.

• 대한전자공학회논문지
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• 제23권4호
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• pp.484-489
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• 1986

A device with variable stepped oxide layer along the edge region of Schottky junction have been designed and fabricated. The effect of this stepped oxide layer in the edge region improves the breakdown voltage as a result of the by increase of the depletion layer width, and decreases the leakage current as compared to the effect of conventional field oxide layer, when the reverse voltage was applied. Experimental results shown that the Schottky diode with the the reverse voltage was applied. Experimenal results show that the Schottky diode with the optimal stepped oxide layer maintains nearly ideal I-V characteristics and excellent breakdown voltage(170V) by reducing the edge effect inherent in metal-semiconductor contacts. The optimal conditions of stepped oxide layer are 1700\ulcornerin thickness and 10\ulcorner in length.

• 전자공학회논문지
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• 제50권7호
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• pp.109-114
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• 2013

전력 MOSFET(산화물-반도체 전위 효과 트랜지스터)는 BLDC 모터와 전력 모듈 등에 광범위하게 사용하고 있다. 기존 전력 MOSFET 구조는 온-저항과 항복전압사이에 절충(tradeoff)이 필요하다. 이러한 절충을 하지 않고 최적화를 하기위해 비균일 초접합 트랜치 MOSFET 를 설계하는데 동일한 항복전압에서 균일 초접합 트랜치 MOSFET보다 낮은 온-저항을 갖도록한다. 이를 위해 드리프트 영역에서 우수한 전기장 분포를 달성하기 위하여 선형구조의 도핑 프로파일을 제안하고, 단위 셀 설계, 도핑농도의 특성분석, 전위분포를 SILVACO TCAD 2D인 Atlas 소자 소프트웨어를 사용하여 시뮬에이션을 수행하였다. 결과로 100V 급 MOSFET에서 비균일 초접합 트랜치 MOSFET가 균일 초접합 트랜치 MOSFET보다 온-저항에서 우수한 특성을 보여주고 있다.