• 전기전자학회논문지
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• 제26권4호
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• pp.705-709
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• 2022

Poly(vinylidene fluoride-trifluoroethylene)(P(VDF-TrFE)) 고체 전해질 층의 어닐링 온도가 고분자 멤리스터의 전기적 특성에 미치는 영향을 분석하였다. 형태적 분석에서 100℃ 어닐링 온도를 갖는 P(VDF-TrFE) (100P(VDF-TrFE)) 박막 대비 200℃ 어닐링 온도를 갖는 P(VDF-TrFE) (200P(VDF-TrFE)) 박막의 표면 거칠기가 약 5배 크고 두께는 약 20% 작은 것으로 나타났다. 100P(VDF-TrFE)를 갖는 멤리스터 (M100) 대비 200P(VDF-TrFE) 멤리스터 (M200)의 set voltage는 약 50% 감소하였고, reset voltage의 크기는 약 30% 증가하였다. 또한, M200이 M100보다 더 나은 메모리 유지 특성을 갖는 것으로 나타났다. 이러한 차이는 M100 대비 M200 내부의 강한 국소 전기장 때문인 것으로 판단된다. 본 연구는 고분자 멤리스터의 어닐링 온도의 중요성을 제시함에 의의가 있다.

• Transactions on Electrical and Electronic Materials
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• 제11권3호
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• pp.106-111
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• 2010

The convergence of significantly different and disparate technologies such as spintronics, carbon nano tube field effect transistors, photon and bio-responsive molecular switches, memristor and memristive systems and metamaterials, coupled with energy scavenging sources are gaining a renewed focus in the quest for new products. This paper will provide an insight into an anticipated technological revolution and will highlight a futuristic Roadmap to capture opportunities that are brought about as the results of formulation of new circuit components basically driven by emergence of nanoscale materials as part of System on System integration. Challenges as the result of new lumped components such as memristor, metamaterial-based lumped components and the like that will challenge the designers' comfort zone will also be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.750-754
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• 2014

Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.

• 전자공학회논문지
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• 제51권9호
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• pp.67-74
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• 2014

본 논문은 멤리스터-CMOS 기반의 잉여 이진 부호화 자리수 (RBSD) 가산기를 제안한다. 기존의 RBSD 가산기는 리플 캐리 가산기에 비해 큰 면적을 차지한다. 또한 처리하는 비트 수가 적을 때 연산 속도가 느린 단점이 있다. 제안된 RBSD 가산기는 기존 RBSD 가산기의 단점을 보완하기 위해 멤리스터-CMOS 회로를 사용한다. 제안된 멤리스터-CMOS 기반의 RBSD 가산기는 기존 RBSD 가산기에 비해 단위 셀 면적이 45% 감소하였고, 지연시간이 24% 감소하였다. 제안된 멤리스터-CMOS 기반의 RBSD 가산기의 구현으로 인해 RBSD 가산기의 장점이 더욱 부각되고, 대용량 회로에서 더 큰 이득을 얻는다.

• 전자공학회논문지
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• 제51권10호
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• pp.64-71
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• 2014

곱셈기는 멀티미디어 통신 시스템과 같이 다양한 신호처리 알고리즘을 갖는 복잡한 연산을 수행한다. 곱셈기는 상대적으로 큰 전달 지연시간, 높은 전력 소모, 큰 면적을 갖는다. 이 논문은 멤리스터-CMOS 기반의 재구성 가능한 곱셈기를 제안하여 곱셈기 회로의 면적을 줄이고 다양한 응용프로그램에 최적화 된 비트폭을 제공한다. 멤리스터-CMOS 기반의 재구성 가능한 곱셈기의 성능은 1.8 V 공급전압에서 멤리스터 SPICE 모델과 180 nm CMOS 공정으로 검증했다. 검증 결과 제안한 멤리스터-CMOS 기반의 재구성 가능한 곱셈기는 종래의 것과 비교시 면적, 지연시간, 전력소모가 각각 61%, 38%, 28% 개선되었고, twin-precision 곱셈기와 면적 비교에서도 22% 개선되었다.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.1-6
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• 2024

Recently, artificial neural networks have been playing a crucial role and advancing across various fields. Artificial neural networks are typically categorized into feedforward neural networks and recurrent neural networks. However, feedforward neural networks are primarily used for processing static spatial patterns such as image recognition and object detection. They are not suitable for handling temporal signals. Recurrent neural networks, on the other hand, face the challenges of complex training procedures and requiring significant computational power. In this paper, we propose memristors suitable for an advanced form of recurrent neural networks called reservoir computing systems, utilizing a mask processor. Using the characteristic equations of Ti/TiOx/TaOy/Pt, Pt/TiOx/Pt, and Ag/ZnO-NW/Pt memristors, we generated current-voltage curves to verify their memristive behavior through the confirmation of hysteresis. Subsequently, we trained and inferred reservoir computing systems using these memristors with the NIST TI-46 database. Among these systems, the accuracy of the reservoir computing system based on Ti/TiOx/TaOy/Pt memristors reached 99%, confirming the Ti/TiOx/TaOy/Pt memristor structure's suitability for inferring speech recognition tasks.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.174-179
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• 2017

We designed the CMOS analog integrate and fire (I&F) neuron circuit for driving memristor based on resistive-switching random access memory (RRAM). And we fabricated the RRAM device that have $HfO_2$ switching layer using atomic layer deposition (ALD). The RRAM device has gradual set and reset characteristics. By spice modeling of the synaptic device, we performed circuit simulation of synaptic device and CMOS neuron circuit. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, two inverters for pulse generation, a refractory part, and finally a feedback part for learning of the RRAM. We emulated the spike-timing-dependent-plasticity (STDP) characteristic that is performed automatically by pre-synaptic pulse and feedback signal of the neuron circuit. By STDP characteristics, the synaptic weight, conductance of the RRAM, is changed without additional control circuit.

• 마이크로전자및패키징학회지
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• 제28권4호
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• pp.41-45
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• 2021

본 연구에서는 멤리스터 소자의 높은 신뢰성을 확보하기 위해 소자 제작 단계에서 30 nm 두께의 ZrO₂ 금속산화물 박막 위 국부영역에 리튬 filament seed 층을 패턴하여 작은 이온반경의 리튬이온을 저항변화 주체로 활용하는 멤리스터 소자를 구현하였다. 패턴 된 리튬 filament seed 대비 다양한 상부전극의 면적을 적용하여 멤리스터-커패시턴스 병렬 구조의 이온형 저항변화 소자에서 커패시턴스가 filament type 저항변화 특성에 미치는 영향을 조사하고자 하였다. 이를 위해 ZrO₂ 박막 위에 5 nm 두께, 5 ㎛ × 5 ㎛ 면적의 리튬 filament seed 증착 후 50 ㎛, 100 ㎛ 직경의 상부전극을 증착, 리튬 메탈의 확산을 위한 250℃ 열처리 전 후 샘플에서 저항변화 특성을 확인하였다. 열확산에 의해 형성된 전도성 filament의 경우 전압에 의한 제어가 불가함을 확인하였으며, 전압에 의해 형성된 filament만이 electrochemical migration에 의한 가역적 저항변화 특성 구현이 가능한 것을 확인하였다. 전압에 의한 filament 형성 시 병렬로 존재하는 커패시턴스의 크기가 filament의 형성 및 소실에 중요한 인자임을 확인하였다.

• 한국전기전자재료학회논문지
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• 제35권4호
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• pp.311-321
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• 2022

The report reviews recent research efforts in demonstrating a computing system whose operation principle mimics the dynamics of biological neurons. The temporal variation of the membrane potential of neurons is one of the key features that contribute to the information processing in the brain. We first summarize the neuron models that explain the experimentally observed change in the membrane potential. The function of ion channels is briefly introduced to understand such change from the molecular viewpoint. Dedicated circuits that can simulate the neuronal dynamics have been developed to reproduce the charging and discharging dynamics of neurons depending on the input ionic current from presynaptic neurons. Key elements include volatile memristors that can undergo volatile resistance switching depending on the voltage bias. This behavior called the threshold switching has been utilized to reproduce the spikes observed in the biological neurons. Various types of threshold switch have been applied in a different configuration in the hardware demonstration of neurons. Recent studies revealed that the memristor-based circuits could provide energy and space efficient options for the demonstration of neurons using the innate physical properties of materials compared to the options demonstrated with the conventional complementary metal-oxide-semiconductors (CMOS).

• Transactions on Electrical and Electronic Materials
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• 제11권6호
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• pp.243-248
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• 2010

The emergence of different and disparate materials together with the convergence of both the 'old' and 'emerging' technologies is paving the way for integration of heterogeneous technologies that are likely to extend the limitations of silicon technology beyond the roadmap envisaged for complementary metal-oxide semiconductor. Formulation of new information processing concepts based on novel aspects of nano-scale based materials is the catalyst for new nanoarchitectures driven by a different perspective in realization of novel logic devices. The memory technology has been the pace setter for silicon scaling and thus far has pave the way for new architectures. This paper provides an overview of the inevitability of heterogeneous integration of technologies that are in their infancy through initiatives of material physicists, computational chemists, and bioengineers and explores the options in the spectrum of novel non-volatile memory technologies considered as forerunner of new logic devices.