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http://dx.doi.org/10.5573/ieie.2014.51.10.064

A Reconfigurable Multiplier Architecture Based on Memristor-CMOS Technology  

Park, Byungsuk (College of Electrical and Computer Engineering, Chungbuk National University)
Lee, Sang-Jin (College of Electrical and Computer Engineering, Chungbuk National University)
Jang, Young-Jo (School of Electrical, Electronics & Communication Engineering, Korea University of Technology and Education)
Eshraghian, Kamran (College of Electrical and Computer Engineering, Chungbuk National University)
Cho, Kyoungrok (College of Electrical and Computer Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.10, 2014 , pp. 64-71 More about this Journal
Abstract
Multiplier performs a complex arithmetic operation in various signal processing algorithms such as multimedia and communication system. The multiplier also suffers from its relatively large signal propagation delay, high power dissipation, and large area requirement. This paper presents memristor-CMOS based reconfigurable multiplier reducing area occupation of the multiplier circuitry and increasing compatibility using optimized bit-width for various applications. The performance of the memristor-CMOS based reconfigurable multiplier are estimated with memristor SPICE model and 180 nm CMOS process under 1.8 V supply voltage. The circuit shows performance improvement of 61% for area, 38% for delay and 28% for power consumption respectively compared with the conventional reconfigurable multipliers. It also has an advantage for area reduction of 22% against a twin-precision multiplier.
Keywords
멤리스터-CMOS;곱셈기;재구성 가능한 구조;
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