• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.728-732
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• 2014

Macro-model of magnetic tunnel junction (MTJ) for spin transfer torque magnetic random access memory (STT-MRAM) has been developed. The macro-model can describe the dynamic behavior such as the state change of MTJ as a function of the pulse width of driving current and voltage. The statistical behavior has been included in the model to represent the variation of the MTJ characteristic due to process variation. The macro-model has been developed in Verilog-A.

• 대한전자공학회논문지SD
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• 제40권2호
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• pp.98-103
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• 2003

본 논문에서는 Magnetic Tunnel Junction (MTJ)의 새로운 SPICE Macro-Model에 대해서 제안하였다. 제안된 Macro-Model은 다섯 개의 터미널을 가지고 있으며 MTJ의 MR 특성인 hysteresis 성질을 그대로 구현하고 있으며, 시간에 따라 변하는 입력 신호에 대해서도 정확하게 동작하도록 구성되어 시다. 또한 MTJ의 MR 특성을 파라미터 변수값으로 입력을 받을 수 있도록 하여 MTJ의 특성변화에 대해서도 용이하게 적용될 수 있도록 하였다.

• 공업화학
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• 제16권6호
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• pp.853-856
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• 2005

자성 메모리반도체의 핵심 소자인 magnetic tunnel junction (MTJ) stack에 대한 고밀도 유도결합 플라즈마 반응성 식각이 연구되었다. MTJ stack은 electron(e)-beam lithography 공정을 사용하여 나노미터 크기의 패턴 형성이 되었으며 식각을 위한 하드 마스크(hard mask)로서 TiN 박막이 이용되었다. TiN 박막은 Ar, $Cl_2/Ar$, 그리고 $SF_6/Ar$들의 가스를 사용하여 식각공정이 연구되었다. E-beam lithography로 패턴된 TiN/MTJ stack은 첫 번째 단계로 TiN 하드 마스크가 식각되고 두 번째로 MTJ stack이 식각되어 완성되었다. MTJ stack은 Ar, $Cl_2/Ar$, $BCl_3/Ar$을 이용하여 식각되었으며 각각의 가스농도와 가스 압력을 변화시켜 MTJ stack의 식각특성이 조사되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권3호
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• pp.197-204
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• 2002

DRAM, SRAM, and FLASH memory are three major memory devices currently used in most electronic applications. But, they have very distinct attributes, therefore, each memory could be used only for limited applications. MRAM (Magneto-resistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. To be a commercially competitive memory device, scalability is an important factor as well. This paper is testing the actual electrical parameters and the scaling factors to limit MRAM technology in the semiconductor based memory device by an actual integration of MRAM core cell. Electrical tuning of MOS/MTJ, and control of resistance are important factors for data sensing, and control of magnetic switching for data writing.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.943-946
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• 2003

This paper proposes new SPICE Macro-Model of MTJ(Magnetic Tunnel Junction). This Macro-Model has five I/O terminals, reproduces MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.458-464
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• 2017

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

• Journal of Magnetics
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• 제6권4호
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• pp.126-128
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• 2001

The effect of rapid thermal anneal (RTA) has been investigated on the properties of an FeMn exchange-biased magnetic tunnel junction (MTJ) using magnetoresistance and I-V measurements and transmission electron microscopy (TEM). The tunneling magnetoresistance (TMR) in an as-grown MTJ is found to be ∼27%, while the TMR in MTJs annealed by RTA increases with annealing temperature up to 300$\^{C}$, reaching ∼46%. A TEM image reveals a structural change in the interface of A1$_2$O$_3$layer for the MTJ annealed by RTA at 300$\^{C}$. The oxide barrier parameters are found to vary abruptly with annealing time within a few ten seconds. Our results demonstrate that the present RTA enhances the magnetoresistive properties of MTJs.

• Journal of Magnetics
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• 제7권3호
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• pp.101-105
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• 2002

MRAM (Magnetoresistive Random Access Memory) is a promising candidate for a universal memory that meets all application needs with non-volatile, fast operational speed, and low power consumption. The simplest architecture of MRAM cell is a series of MTJ (Magnetic Tunnel Junction) as a data storage part and MOS transistor as a data selection part. This paper is for testing the actual electrical parameters to adopt MRAM technology in the semiconductor based memory device. The discussed topics are an actual integration of MRAM core cell and its properties such as electrical tuning of MOS/MTJ for data sensing and control of magnetic switching for data writing. It will be also tested that limits of the MRAM technology for a high density memory.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2002년도 동계연구발표회 논문개요집
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• pp.60-61
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• 2002

현재 Magnetic Tunnel Junction는 고밀도 자기저항 헤드 및 비휘발성 메모리(MRAM)등의 자기저항 특성을 이용한 소자에 응용하기 위해 많은 연구가 진행되고 있다[1]. 하지만 Magnetic Tunnel Junction(MTJ)을 실제 소자로서 제작하여 사용하기 위해서는 smooth하고 pinhole이 없으며, 절연층 내부에 disorder나 defect가 없는 절연층을 형성해야 한다. (중략)

• 대한전자공학회논문지SD
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• 제45권8호
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• pp.1-10
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• 2008

본 논문에서는 새로운 스위칭 방식인 LFS (Local Field Switching)을 이용하여 설계한 128비트 MRAM (Magnetoresistive Random Access Memo교)에 대해 기술하였다. LFS 방식은 MTJ (Magnetic Tunnel Junction)를 직접 통과해 흐르는 전류에 의해 형성되는 국소 자기장을 이용하여 MTJ의 극성을 변환시킨다. 이 방식은 MTJ와 전류의 거리가 가깝기 때문에 작은 전류로도 충분히 큰 자기장을 형성하므로 writing current가 적어도 된다. 또한 Digit Line이 없어도 되므로 half select disturbance가 발생하지 않아 기존 MTJ를 이용한 방식에 비해 셀 선택도가 우수하다. 설계한 MRAM은 IT(트랜지스터)-1MTJ의 메모리 셀 구조를 가지며 양방향 write driver와 mid-point reference cell block, current mode sense amplifier를 사용한다. 그리고 MTJ 공정 없이 회로 동작을 확인하기 위해 LFS-MTJ cell을 CMOS emulation cell로 대체하였다. 설계한 회로를 6 metal을 사용하는 $0.18{\mu}m$ CMOS 공정으로 구현하였고 제작된 chip을 custom board 상에서 테스트하여 동작을 확인하였다.