JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

Variation-tolerant Non-volatile Ternary Content Addressable Memory with Magnetic Tunnel Junction

  • Cho, Dooho (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Kim, Kyungmin (Department of Electronics and Computer Engineering, Hanyang University) ;
  • Yoo, Changsik (Department of Electronics and Computer Engineering, Hanyang University)
  • Received : 2017.03.06
  • Accepted : 2017.06.12
  • Published : 2017.06.30
Download PDF
⟨ Previous Next ⟩

Abstract

A magnetic tunnel junction (MTJ) based ternary content addressable memory (TCAM) is proposed which provides non-volatility. A unit cell of the TCAM has two MTJ's and 4.875 transistors, which allows the realization of TCAM in a small area. The equivalent resistance of parallel connected multiple unit cells is compared with the equivalent resistance of parallel connected multiple reference resistance, which provides the averaging effect of the variations of device characteristics. This averaging effect renders the proposed TCAM to be variation-tolerant. Using 65-nm CMOS model parameters, the operation of the proposed TCAM has been evaluated including the Monte-Carlo simulated variations of the device characteristics, the supply voltage variation, and the temperature variation. With the tunneling magnetoresistance ratio (TMR) of 1.5 and all the variations being included, the error probability of the search operation is found to be smaller than 0.033-%.

Keywords

References

  1. M. Meribout, T. Ogura, and M. Nakanishi, "On using the CAM concept for parametric curve extraction," Image Processing, IEEE Transactions on, Vol.9, No.12, pp.2126-2130, Dec., 2000. https://doi.org/10.1109/83.887981
  2. M. Nakanishi and T. Ogura, "Real-time CAM-based Hough transform and its performance evaluation," Pattern Recognition, Proceedings, 13th IEEE International Conference on, Vol.2, pp.516-521, 1996.
  3. V. C. Ravikumar, R. N. Mahapatra and L. N. Bhuyan, "EaseCAM: An Energy and Storage Efficient TCAM-based Router Architecture for IP Lookup," Computers, IEEE Transactions on, Vol.54, No.5, pp.521-533, May, 2005. https://doi.org/10.1109/TC.2005.78
  4. K. Pagiamtzis and A. Sheikholeslami, "Content-Addressable Memory (CAM) Circuits and Architectures: A Tutorial and Survey," Solid-State Circuits, IEEE Journal of, Vol.41, No.3, pp.712- 727, Mar., 2006. https://doi.org/10.1109/JSSC.2005.864128
  5. Y. Zhang, W. Zhao, J. O. Klein, D. Ravelsona and C. Chappert, "Ultra-High Density Content Addressable Memory Based on Current Induced Domain Wall Motion in Magnetic Track," Magnetics, IEEE Transactions on, Vol.48, No.11, pp.3219-3222, Nov., 2012. https://doi.org/10.1109/TMAG.2012.2198876
  6. M. K. Gupta and M. Hasan, "Design of High-Speed Energy-Efficient Masking Error Immune PentaMTJ-Based TCAM," Magnetics, IEEE Transactions on, Vol.51, No.2, Feb., 2015.
  7. S. Matsunaga, et al., "Fully Parallel 6T-2MTJ nonvolatile TCAM with single-transistor-based self match-line discharge control," VLSI Circuits, IEEE Symposium 2011, Digest of Technical Papers, pp.289-290., 2011.
  8. S. Matsunaga, et al., "A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture," VLSI Circuits, IEEE Symposium 2012, Digest of Technical Papers, pp.44-45., 2012.
  9. T. Hanyu, et al., "Spintronics-Based Nonvolatile Logic-in-Memory Architecture Towards an Ultra-Low-Power and Highly Reliable VLSI Computing Paradigm," Design, Automation & Test, IEEE 2015 Europe Conference & Exhibition, pp.1006-1011, 2015.
  10. M. K. Gupta and M. Hasan, "Robust High Speed Ternary Magnetic Content Addressable Memory," Electron Devices, IEEE Transactions on, Vol.62, No.4, pp.1163-1169, Apr., 2015. https://doi.org/10.1109/TED.2015.2398122
  11. B. Song, T. Na, J. P. Kim, S. H. Kang and S. O. Jung, "A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and Compact Area," Circuits and Systems II: Express Briefs, IEEE Transactions on, 2016.
  12. K. Kim and C. Yoo, "Macro-model of magnetic tunnel junction for STT-MRAM including dynamic behavior," Semiconductor Technology and Science, IEIE Journal of, Vol.14, No.6, pp.728-732, Dec., 2014. https://doi.org/10.5573/JSTS.2014.14.6.728
  13. I. Arsovski and R. Wistort, "Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance content- addressable memories," Proceedings, IEEE 2006 Custom Integrated Circuits Conference, pp. 453-456, 2006.
  14. I. Hayashi, et al., "A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 650-nm CMOS," Solid-State Circuits, IEEE Journal of, Vol.48, No.11, pp.2671-2680, Nov., 2013. https://doi.org/10.1109/JSSC.2013.2274888