• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.7
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• pp.993-1000
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• 2018

This paper proposes a low-dropout voltage regulator(LDO) using self-cascode structure. The self-cascode structure was optimized by adjusting the channel length of the source-side MOSFET and applying a forward voltage to the body of the drain-side MOSFET. The self-cascode of the input differential stage of the error amplifier is optimized to give higher transconductance, but the self-cascode of the output stage is optimized to give higher output resistance, The proposed LDO using self-cascode structure was designed by a $0.18{\mu}m$ CMOS technology and simulated using SPECTRE. The load regulation of the proposed LDO regulator was 0.03V/A, whereas that of the conventional LDO was 0.29V/A. The line regulation of the proposed LDO regulator was 2.23mV/V, which is approximately three times improvement compared to that of the conventional LDO. The transient response of the proposed LDO regulator was 625ns, which is 346ns faster than that of the conventional LDO.

• Journal of IKEEE
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• v.19 no.4
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• pp.506-513
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• 2015

In this paper, an output-capacitorless, low-dropout (LDO) regulator is designed, which consumes $4.5{\mu}A$ quiescent current. Proposed LDO regulator is realized using two amplifier for good load regulation and fast response time, which provide high gain, high bandwidth, and high slew rate. In addition, a one-shot current boosting circuit is added for current control to charge and discharge the parasitic capacitance at the pass transistor gate. As a result, response time is improved during load-current transition. The designed circuit is implemented through a $0.11-{\mu}m$ CMOS process. We experimentally verify output voltage fluctuation of 260mV and recovery time of $0.8{\mu}s$ at maximum load current 200mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2729-2734
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• 2011

In this paper, an active replica Low-dropout(LDO) regulator with DC voltage matching circuit is presented. In order to match the voltage between replica and output of regulator, DC voltage matching circuit is designed. The active replica low dropout regulator has higher Power Supply Rejection(PSR) than that of conventional regulator. The designed DC voltage matching circuit can reduce the drawback that may be occurred in replica regulator. And using fully active element in regulator can reduce the chip area and heat noise with resistor. As results of HSPICE simulation with 0.35um CMOS parameter, the designed active replica LDO regulator achieves Power Supply Rejection, -28@10Hz better than -17@10Hz of conventional replica regulator without DC matching circuit. And the output voltage is 3V.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1673-1681
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• 2015

A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.

• Transactions on Electrical and Electronic Materials
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• v.17 no.3
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• pp.172-177
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• 2016

Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100^o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

• Journal of IKEEE
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• v.21 no.2
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• pp.154-157
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• 2017

This paper proposes the Low-Dropout regulator with two output. Each of the two output has feedback, and shared feedback loop. PMOS is added to solve the problem the occur when sharing the feedback loop. Thus eased the Load Transient Response. Also Using one of the bias citcuit and one of the pass transistor, Area is reduce by half compared to Existing Area that used to obtain output of two output.

• Journal of IKEEE
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• v.21 no.3
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• pp.264-267
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• 2017

In this paper, A low dropout (LDO) regulator that improves the power supply rejection ratio by using a noise canceling circuit is proposed. The noise rejection circuit between the error amplifier and the pass transistor is designed to reduce the influence of the pass transistor on the noise coming from the voltage source. The LDO regulator has the same regulation characteristics as the conventional LDO regulator. The proposed circuit uses 0.18um process and Cadence's Virtuoso and Specter simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.34-40
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• 2011

This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.624-628
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• 2000

In this paper, the phenomenon to show in CDMA handset in case of which CDMA handset do not meet Traffic Rho value of IS-98B specifications, which have minimum requirements of CDMA handset about electrical performance is analyzed. This paper proposed method to improve Traffic Rho through improving the matching circuit of TX IF SAW FILTER and deleting noise of LDO(Low Dropout Regulator) to generate 3.OV_TX in TX block. HP8924C(CDMA Mobile Station Tester Set) and HP8595E(Spectrum Analyzer) measures the improved CDMA waveform.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2503-2510
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• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.