Browse > Article

LDO Linear Regulator Using Efficient Buffer Frequency Compensation  

Choi, Jung-Su (Silicon Mitus)
Jang, Ki-Chang (School of Electrical and Computer Engineering, University of seoul)
Choi, Joong-Ho (School of Electrical and Computer Engineering, University of seoul)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.11, 2011 , pp. 34-40 More about this Journal
Abstract
This paper presents a low-dropout (LDO) linear regulator using ultra-low output impedance buffer for frequency compensation. The proposed buffer achieves ultra low output impedance with dual shunt feedback loops, which makes it possible to improve load and line regulations as well as frequency compensation for low voltage applications. A reference control scheme for programmable output voltage of the LDO linear regulator is presented. The designed LDO linear regulator works under the input voltage of 2.5~4.5V and provides up to 300mA load current for an output voltage range of 0.6~3.3V.
Keywords
LDO Linear regulator; LDO; Ultra-Low Output Impedance Buffer; Reference Control Scheme;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Yi Wang and Lenian He, "A CMOS low-dropout regulator with 3.3uA quiescent current independent of off-chip capacitor," IEEE Asia Pacific Conference of Circuit and Systems, Macao, China, pp. 1320-1323, Nov. 2008.
2 G. A. Rincon-Mora and P. E. Allen, "A low-voltage, low quiescent current, low drop-out regulator," IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36-44, Jan. 1998.   DOI   ScienceOn
3 M. Al-Shyoukh, R. A. Perez, and H. Lee, "A Transient-enhanced low-dropout regulator with buffer impedance attenuation," IEEE J. Soled-State Circuits, vol. 42, no. 8, pp. 1732-1742, Aug. 2007.
4 G. A. Rincon-Mora "Current Efficient, Low Voltage, Low Drop-out Regulators," Ph.D Thesis, Georgia Institute of Technology, Nov. 1996.
5 Mahattanakul, J., "Design procedure for two-stage CMOS operational amplifiers employing current buffer", IEEE Trans. Circuits Syst. II, vol. 52, no. 11, pp. 766-770, Now. 2005.
6 G. A. Rincon-Mora and P. E. Allen, "Optimized frequency-shaping circuit topologies for LDO's," IEEE Trans. Circuit Syst. II, Analog Digital Signal Processing, vol. 45, no. 6, pp. 703-708, Jun. 1998.   DOI   ScienceOn
7 K. N. Leung and P. K. T. Mok, "A capacitor-free CMOS low-dropout regulator with damping factor control frequency compensation," IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691-1702, Oct. 2003.   DOI   ScienceOn
8 C. K. Chava and J. Silva-Martinez, "A frequency compensation scheme for LDO voltage regulators," IEEE Trans. Circuits System. I , Reg. Papers, vol. 51, no. 6, pp. 1041-1050, Jun. 2004.   DOI   ScienceOn