• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.903-906
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• 2003

In this paper, we proposed high slew-rate and low-power OP-AMP of the data driver for TFT-LCDs. Proposed OP-AMP contains newly developed rail-to-rail class-AB input circuit which enables the low-quiescent current and high slew-rate OP-AMP. The slew-rate and the quiescent current of the proposed OP-AMP are 31.2V/$\mu$sec and 5$\mu$A, respectively.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.530-532
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• 2002

We have developed a low-power, high slew-rate OP-AMP for large size and high resolution TFT-LCDs which have 8${\mu}$A quiescent current with settling time less than 6${\mu}$sec. The proposed OP-AMP contains newly developed the driving circuit of class-AB output stage which can achieve a low quiescent current less than 8${\mu}$A and a slew-rate higher than 3.14V/${\mu}$sec.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2000년도 제1회 학술대회 논문집
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• pp.17-18
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• 2000

A low-power source driver for TFT-LCDs has been proposed using the triple charge sharing method that enhances the AC power saving efficiency of the prior charge sharing method. The AC power saving efficiency of the proposed source driver reaches 66.6%. In addition, a novel OP-AMP with low-quiescent current has been developed. The measured quiescent current of the OP-AMP is $5{\mu}A{\sim}7{\mu}A$ at VDD=5V and VSS=0V with load resistance of $2k{\Omega}$ and load capacitance of 300pF.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.513-514
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• 2006

As power supply managements become more important than before, supplying a stable system voltage is becoming more and more critical. In this study we propose to use the advantage of weak inversion region of MOS transistors. Analog system, which uses weak inversion region, could work in low voltage environment and reduce power consumption. The proposed buck-converter in weak inversion region of MOS transistor has been verified by silicon chip.

• 전기전자학회논문지
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• 제19권4호
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• pp.506-513
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• 2015

본 논문에서는 외부 커패시터가 없는 low-dropout (LDO) 레귤레이터를 설계하였으며, 대기 전류는 $4.5{\mu}A$ 이다. 제안하는 LDO 레귤레이터는 정밀한 로드 레귤레이션과 빠른 응답 속도를 만족하기 위해 두 개의 증폭기를 사용 하였고, 높은 이득을 갖는 증폭기와 빠른 속도 및 높은 슬루율을 가지는 증폭기로 구성 되어 있다. 이와 함께 패스 트랜지스터의 게이트에 존재하는 큰 기생 커패시터에 전류를 빠르게 충 방전시키기 위해, 전류 부스팅 회로를 추가하였다. 이를 통해 부하 전류 변화 시 응답 시간을 향상 시키게 된다. 설계된 회로는 $0.11-{\mu}m$ CMOS 공정으로 제작되었다. 최대 200mA 의 부하 전류를 구동할 수 있으며, 출력 전압 변동은 260mV, 회복 시간은 $0.8{\mu}s$ 을 측정하였다.

• ETRI Journal
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• 제42권5호
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• IEIE Transactions on Smart Processing and Computing
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• 제4권5호
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.263-271
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• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.905-908
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• 2005

본 논문에서는 class AB opamp 를 채용한 384kHz differential PWM 신호를 입력으로 하는 2-channel stereo audio amplifier 블록을 공급전압 3.3V 조건에서 SMIC 0.18um thick oxide 기술을 이용하여 설계한다. 여기서 class AB opamp 는 공정 변화에 따른 quiescent current가 변하는 것을 최소화하기 위하여 adaptive load 를 사용하며, 전체적으로는 3 차 Butterworth lowpass filter 와 differential-to-single converter 로 구성된 2 개의 audio amplifier 와 출력전압이 ${\frac{1}{2}}Vdd$ 인 common output 블록으로 구성된다. 이러한 설계를 통하여 32ohm 의 저항 load 를 구동할 수 있는 -60dB THD, 전체 quiescent current 2mA 대인 CMOS class AB stereo audio amplifier 를 구현하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.