• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.281-284
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• 2003

Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

• Journal of Information Display
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• v.6 no.4
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• Progress in Superconductivity and Cryogenics
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• v.8 no.2
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• pp.17-19
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• 2006

A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.1
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• pp.28-34
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• 2007

In this research, the characteristics of the DC discharge that was the logical gate input of discharge logic gate PDP newly proposed was considered. The logical output is induced by controlling the potential difference of inter-electrode according to the discharge path in the discharge logic gate. From the experimental result the discharge time lag was shortened to 1/3 and the voltage has decreased to 1/2 in the case to apply priming discharge for improving stability of these DC discharges compared with the case when it is not applied. Moreover, after the priming discharge ends, the space charge generated by this discharge influences it up to about $30[{\mu}s]$. And, as a measured result of the influence that the space charge exerts on the DC discharge with the change in time and spatial distance, it has been understood that there is a possibility that going away spatially can slip out the influence of the discharge easily as for going away from the discharge time-wise. Therefore the conclusion that the discharge logic gates of each scanning electrode can be operated independently is obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.622-634
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• 2013

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.1-6
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• 2014

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.

• Journal of Advanced Navigation Technology
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• v.20 no.6
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• pp.631-637
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• 2016

Quantum cellular automata (QCA) are one of the alternative technologies that can overcome the limits of complementary metal-oxide-semiconductor (CMOS) scaling. It consists of nano-scale cells and demands very low power consumption. Various circuits on QCA have been researched until these days, and in the middle of the researches, exclusive-OR (XOR) gates are used as error detection and recover. Typical XOR logic gates have a lack of scalable, many clock zones and crossover designs so that they are difficult to implement. In order to overcome these disadvantages, this paper proposes XOR design using majority gate reduced clock zone. The proposed design is compared and analysed to previous designs and is verified the performance.