1 |
S. Chakraborty, J. Mekie and D. K. Sharma, "Reasoning about Synchronization Issues in GALS Systems: A Unified Approach", invited paper in Proc. of Workshop on Formal Methods in GALS Architectures (FMGALS), Formal Methods Europe Symposium, Sept 2003
|
2 |
J.K. Park, J.H. Lim, S.M Lee, W. Cho, G. Moon, "The effect analysis of signal synchronization for bias current and josephson junction size of superconductive digital SFQ circuits", in Proc. KIASC 2004 Conf. Circuits and Systems Theory, MuJu, 2004. pp. 151-153
|
3 |
Z.J. Deng, N. Yoshikawa, S.R. Whiteley and T. Van Duzer, "Data-driven self-timed RSFQ high-speed test system", IEEE Trans. Appl. Supercond., vo7.4, pp. 3830-3833, Dec 1997
DOI
ScienceOn
|
4 |
Z.J. Deng, N. Yoshikawa, S.R. Whiteley and T. Van Duzer, "Data-driven self-timed RSFQ digital integrated circuit and system", IEEE Trans. Appl. Supercond., vo7.2, pp.3634-3637, June 1997
DOI
ScienceOn
|
5 |
T. Van Duzer, Charles W. Turner, Principles of Superconductive Devices and Circuits, Upper saddle river NJ 07458: Prentice Halt PTR, 1999, pp. 283-325
|
6 |
S.M. Lee, W. Cho, J.K. Park, J.H. Lim, G. Moon, "Delay time analysis of self-timing-aligned clock synchronization of superconductive digital SFQ through Mo resistance variation", in Proc. KIASC 2004 Conf. Circuits and Systems Theory, MuJu, 2004. pp.154-157
|
7 |
K. K. Likarev and V. K. Semenov, "RSFQ Logic/Memory Family: A new Josephson Junction Technology for sub-Terahertz Frequency Clock Digital Systems," IEEE Trans. Appl. Supercond., vol.1, pp.13-28, March 1991
|