Browse > Article
http://dx.doi.org/10.5573/JSTS.2010.10.3.176

Inductorless 8.9 mW 25 Gb/s 1:4 DEMUX and 4 mW 13 Gb/s 4:1 MUX in 90 nm CMOS  

Sekiguchi, Takayuki (Solutions Research Laboratory, Tokyo Institute of Technology)
Amakawa, Shuhei (Solutions Research Laboratory, Tokyo Institute of Technology)
Ishihara, Noboru (Solutions Research Laboratory, Tokyo Institute of Technology)
Masu, Kazuya (Solutions Research Laboratory, Tokyo Institute of Technology)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.10, no.3, 2010 , pp. 176- 184 More about this Journal
Abstract
A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.
Keywords
MUX; DEMUX; low-power; high-speed; CMOS logic circuit; pseudo-NMOS;
Citations & Related Records

Times Cited By SCOPUS : 1
연도 인용수 순위
1 S. Henzler and S. Koeppe, “Design and application of power optimized high-speed CMOS frequency dividers,” IEEE Trans. VLSI Syst., Vol.16, No.11, pp.1513-1520, Nov., 2008.   DOI   ScienceOn
2 K. Kanda, D. Yamazaki, T. Yamamoto, M. Horinaka, J. Ogawa, H.Tamura, and H. Onodera, “40 Gb/s 4:1 MUX/1:4 DEMUX in 90 nm standard CMOS,” ISSCC Dig. Tech. Papers, pp.152-153, Feb., 2005.
3 K. Kanda, D. Yamazaki, T. Yamamoto, M. Horinaka, J. Ogawa, H. Tamura, and H. Onodera, “40 Gb/s 4:1 MUX/1:4 DEMUX in 90 nm standard CMOS technology,” IEICE Tech. Rep., VLD2005- 55, pp.7-14, 2005 (in Japanese).
4 J. P. Uyemura, CMOS Logic Circuit Design, Kluwer Academic Publishers, 2001.
5 W. J. Dally and J. W. Poulton, Digital Systems Engineering Cambridge University Press, 1998.
6 H.-D.Wohlmuth, D.Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” European Solid-State Circuits Conference, pp.823-826, Sep., 2002.
7 A. Tanabe, M. Umetani, I. Fujiwara, T. Ogura, K. Kataoka, M. Okihara, H. Sakuraba, T. Endoh, and F. Masuoka, “A 10 Gb/s demultiplexer IC in 0.18 ${\mu}m$ CMOS using current mode logic with tolerance to the threshold voltage fluctuation,” ISSCC Dig. Tech. Papers, pp.62-63, Feb., 2000.
8 B.-G. Kim, L.-S. Kim, S. Byun, and H.-K. Yu, “A 20 Gb/s 1:4 DEMUX without inductors in 0.13 ${\mu}m$ CMOS,” ISSCC Dig. Tech. Papers, pp.528-529, Feb., 2006.
9 D. Kehrer, H.-D. Wohlmuth, H. Knapp, M. Wurzer, and A. L. Scholtz, “40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS,” ISSCC Dig. Tech. Papers, pp.344-345, Feb., 2003.
10 D. Kehrer and H.D.Wohlmuth., “30-Gb/s 70-mW One-Stage 4:1 Multiplexer in 0.13 ${\mu}m$ CMOS,” IEEE J. Solid-State Circuits, pp.1140-1147, 2004.   DOI   ScienceOn
11 J. Lee, J.Y. Ding, and T.Y. Cheng., “A 20-Gb/s 2-to-1 MUX and a 40-GHz VCO in 0.18-${\mu}m$ CMOS Technology,” VLSI Circuits Dig. Tech. Papers, pp.136-139, 2005.
12 D. Kehrer, H.D. Wohlmuth, C. Kienmayer, and A. Scholtz., “A 1 V Monolithic Transformer-Coupled 30-Gb/s 2:l Multiplexer in 120 nm CMOS,” IEEE MTT-S Int. Microwave Symp. Dig., pp.2261-2264, 2003.
13 D. H. Kim, S. Mukhopadhyay, and S. K. Lim, “TSV-aware interconnect length and power prediction for 3D stacked ICs,” Proc.International Interconnect Technology Conf., pp.26-28, 2009.
14 M. Anis, M. Allam, and M. Elmasry, “Impact of technology scaling on CMOS logic styles,” IEEE Trans. Circuits Syst. II, Vol.49, No.8, pp.577-588, Aug., 2002.   DOI
15 M. Yamashina and H. Yamada, “An MOS current mode logic (MCML) circuit for low-power sub-GHz processors,” IEICE Trans.Electron., Vol. E75-C, No.10, pp.1181-1187, Oct., 1992.
16 Y. Liu, J. Quan, H. Yang, and H. Wang, “MOS current mode logic circuits: Design consideration in high-speed low-power applications and its future trend, a tutorial,” International J. High Speed Electronics and Systems, Vol.15, No.3, pp.599-614, Sep., 2005.   DOI   ScienceOn
17 A. Mineyama, T. Suzuki, H. Ito, S. Amakawa, N. Ishihara, and K. Masu, “A 20 Gb/s 1:4 DEMUX with near-rail-to-rail logic swing in 90 nm CMOS process,” IEEE International Workshop Series on Signal Integrity and High-Speed Interconnects, pp.119-122, Feb., 2009.