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http://dx.doi.org/10.9723/jksiis.2014.19.6.001

Delay Insensitive Asynchronous Circuit Design Based on New High-Speed NCL Cells  

Kim, Kyung Ki (대구대학교 전자전기공학부)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.19, no.6, 2014 , pp. 1-6 More about this Journal
Abstract
The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.
Keywords
Delay insensitive asynchronous circuit; NCL; Null convention logic;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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