• Transactions on Electrical and Electronic Materials
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• v.13 no.3
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• pp.162-164
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• 2012

In this study, we fabricate Pt nanoparticle (NP)-embedded MOS capacitors at room temperature and investigate their memory characteristics. The Pt NPs are separated from each other and situated between the tunnel and control oxide layers. The average size and density of the Pt NPs are 4 nm and $3.2{\times}10^{12}cm^{-2}$, respectively. Counterclockwise hysteresis with a width of 3.3 V is observed in the high-frequency capacitance-voltage curve of the Pt NP-embedded MOS capacitor. Moreover, more than 93% of the charge remains even after $10^4$ s.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.3
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1395-1397
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• 1996

Many of the existing neural associative memories are trained and recalled in separate modes and are not suitable for temporal pattern storage and classification in that user must specify the time and length of input patterns. In this paper, a new on-line temporal associative memory model is presented. This memory is structured in layers of neurons and each neuron has limited number of weights so that calculation complexity can be considerably reduced and processing of patterns can be achieved in real time.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.08a
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• pp.130-130
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• 2008

• 한국생물공학회:학술대회논문집
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• 2003.10a
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• pp.209-213
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• 2003

Self-assembled monolayers of spinach ferredoxin immobilized to Au substrate were investigated. Ferredoxin was immobilized onto the chemically modified Au surface. Au surface were modified to $NH^{3+}$ by the 4-aminothiphenol and then modified by N-succinimidyl-3-[2-pyridyldithio]propionate for the ferredoxin immobilization. To verify the electrochemical activity of immobilized ferredoxin molecules, cyclic-voltammetry was measured. Finally, to verify the memory application, reduction potential was applied to ferredoxin molecules as for the write function, and then current transients observed from the reduced ferredoxin layers were measured for the read function of memory applications.

• Journal of the Semiconductor & Display Technology
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• v.19 no.2
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• pp.72-76
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• 2020

The author demonstrated organic ferroelectric thin-film transistors with ferroelectric materials of P(VDF-TrFE) and an amorphous oxide semiconducting In-Ga-Zn-O channel on the silicon substrates. The organic ferroelectric layers were deposited on an oxide semiconductor layer by Langmuir-Blodgett method and then annealed at 128℃ for 30min. The carrier mobility and current on/off ratio of the memory transistors showed 9 ㎠V^-1s^-1 and 6 orders of magnitude, respectively. We can conclude from the obtained results that proposed memory transistors were quite suitable to realize flexible and werable electronic applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.30-36
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• 2011

Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.3-4
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• 2005

Germanium nanocrystals(NCs) were formed in the silicon dioxide($SiO_2$) on Si layers by Ge implantation and rapid thermal annealing process. The density and mean size of Ge-NCs heated at $800^{\circ}C$ during 10 min were confirmed by High Resolution Transmission Electron Microscopy. Capacitance versus voltage(C-V) measurements of MOS capacitors with single $Al_2O_3$ capping layers were performed in order to study electrical properties. The C-V results exhibit large threshold voltage shift originated by charging effect in Ge-NCs, revealing the possibility that the structure is applicable to Nano Floating Gate Memory(NFGM) devices.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.13-13
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• 2009

We have investigated the fabrication and properties of bendable PZT film formed on plastic substrates for the application in flexible memory. These devices used the PZT active layer formed on $SiO_2/Si$ wafer by sol-gel method with optimized device layouts and Pt electrodes. After etching Pt/PZT/Pt layers, patterned by photolithography process. these layers were transferred on PET plastic substrate using elastomeric stamp. The level of performance that can be achieved approaches that of traditional PZT. devices on rigid bulk wafers.

• Journal of the Korea Society of Computer and Information
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• v.26 no.11
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• pp.1-9
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• 2021

3D-NAND flash memory provides high capacity per unit area by stacking 2D-NAND cells having a planar structure. However, due to the nature of the lamination process, there is a problem that the frequency of error occurrence may vary depending on each layer or physical cell location. This phenomenon becomes more pronounced as the number of write/erase(P/E) operations of the flash memory increases. Most flash-based storage devices such as SSDs use ECC for error correction. Since this method provides a fixed strength of data protection for all flash memory pages, it has limitations in 3D NAND flash memory, where the error rate varies depending on the physical location. Therefore, in this paper, pages and layers with different error rates are classified into clusters through the K-means machine learning algorithm, and differentiated data protection strength is applied to each cluster. We classify pages and layers based on the number of errors measured after endurance test, where the error rate varies significantly for each page and layer, and add parity data to stripes for areas vulnerable to errors to provides differentiate data protection strength. We show the possibility that this differentiated data protection policy can contribute to the improvement of reliability and lifespan of 3D NAND flash memory compared to the protection techniques using RAID-like or ECC alone.