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A Die-matching Method for 3D Memory Yield Enhancement considering Additional Faults during Bonding  

Lee, Joo-Hwan (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Ki-Hyun (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.7, 2011 , pp. 30-36 More about this Journal
Abstract
Three-dimensional (3D) memories using through-silicon vias (TSVs) as vertical bus across memory layers are implemented by many semiconductor companies. 3D memories are composed of known-good-dies (KGDs). If additional faults are arisen during bonding, they should be repaired. In order to enhance the yield of 3D memories with inter-die redundancies, a die-matching method is needed to effectively stack memory dies in a 3D memory. In this paper, a new die-matching method is proposed for 3D memory yield enhancement with inter-die redundancies considering additional faults arisen during bonding. Three boundary-limited conditions are used in the proposed die-matching method; they set bounds to the search spaces for selecting memory dies to manufacture a 3D memory. Simulation results show that the proposed die-matching method can greatly enhance the 3D memory yield.
Keywords
Yield enhancement; Die-matching method; 3D memory; Inter-die redundancy;
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Times Cited By KSCI : 1  (Citation Analysis)
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