• 제목/요약/키워드: interpolating

검색결과 298건 처리시간 0.024초

PIV에서의 보간기법의 평가에 관한 연구 (A Study on the Evaluation of Interpolation Methods in PIV)

  • 최장운;조대한;최민선;이영호
    • Journal of Advanced Marine Engineering and Technology
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    • 제20권4호
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    • pp.90-100
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    • 1996
  • To maintain high spacial accuracy and rapid CPU time in interpolating data from grid to random position or inversely in PIV, proposed many technuques are compared and discussed mainly in terms of interpolating error and computing time. And artificial PIV atmosphere data is furnished by CFD result. First, for interpolation from grid to random position, multiquadric method gives the highest accuracy with the longest CPU time and Taylor series expansion methods give reasonable accuracy with less calculating load. Secondly, the sub-pixel resolution analysis in estimating the coordinates of the maximum correlation coefficients essential in the grey level correlation PIV reveal that 8-neighbours 2nd-order least square interpolation gives utmost accuracy in terms of the real flow conditions.

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PIV에서의 보간기법의 평가에 관한 연구 (A Study on the Evaluation of Interpolation Methods in PIV)

  • 최장운;조대환;최민선;이영호
    • Journal of Advanced Marine Engineering and Technology
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    • 제20권4호
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    • pp.412-412
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    • 1996
  • To maintain high spacial accuracy and rapid CPU time in interpolating data from grid to random position or inversely in PIV, proposed many technuques are compared and discussed mainly in terms of interpolating error and computing time. And artificial PIV atmosphere data is furnished by CFD result. First, for interpolation from grid to random position, multiquadric method gives the highest accuracy with the longest CPU time and Taylor series expansion methods give reasonable accuracy with less calculating load. Secondly, the sub-pixel resolution analysis in estimating the coordinates of the maximum correlation coefficients essential in the grey level correlation PIV reveal that 8-neighbours 2nd-order least square interpolation gives utmost accuracy in terms of the real flow conditions.

A 3.3V 10BIT CURRENT-MODE FOLDING AND INTERPOLATING CMOS AJ D CONVERTER USING AN ARITHMETIC FUNCTIONALITY

  • Chung, Jin-Won;Park, Sung-Yong;Lee, Mi-Hee;Yoon, Kwang-Sub
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 ITC-CSCC -2
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    • pp.949-952
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    • 2000
  • A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

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점군으로부터 형성된 다각곡선망을 보간하는 곡면모델링에 관한 연구 (A Study of a Surface Modeling Interpolating a Polygonal Curve Net Constructed from Scattered Points)

  • 주상윤;전차수
    • 대한산업공학회지
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    • 제21권4호
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    • pp.529-540
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    • 1995
  • The paper deals with a procedure for constructing a composite surface interpolating a polygonal curve mesh defined from 3D scattered points. The procedure consists of a poly-angulation, construction of a curve net, and interpolation of the curve net. The poly-angulation contains a stage that changes a triangular edge net obtained from a triangulation into a poly-angular edge net. A curve net is constructed by replacing edges on the edge net with cubic Bezier curves. Finally, inside of an n-sided polygon is interpolated by n subdivided triangular subpatches. The method interpolates given point data with relatively few triangular subpatches. For an n-sided polygon, our method constructs an interpolant with n subdivided triangular subpatches while the existing triangular surface modeling needs 3(n-2) subpatches. The obtained surface is composed of quartic triangular patches which are $G^1$-continuous to adjacent patches.

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Eulerian-Lagrangian Hybrid Numerical Method for the Longitudinal Dispersion Equation

  • Jun, Kyung-Soo;Lee, Kil-Seong
    • Korean Journal of Hydrosciences
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    • 제5권
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    • pp.85-97
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    • 1994
  • A hybrid finite difference method for the longitudinal dispersion equation, which is based on combining the Holly-Preissmann scheme with fifth-degree Hermite interpolating polynomial and the generalized Crank-Nicholson scheme, is described and comparatively evaluated with other characteristics-based numerical methods. Longitudinal dispersion of an instantaneously-loaded pollutant source is simulated, and computational results are compared with the exact solution. The present method is free from wiggles regardless of the Courant number, and exactly reproduces the location of the peak concentration. Overall accuracy of the computation increases for smaller value of the weighting factor, $\theta$of the model. Larger values of $\theta$ overestimates the peak concentration. Smaller Courant number yields better accuracy, in general, but the sensitivity is very low, especially when the value of $\theta$ is small. From comparisons with the hybrid method using cubic interpolating polynomial and with splitoperator methods, the present method shows the best performance in reproducing the exact solution as the advection becomes more dominant.

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AN INTERPOLATING HARNACK INEQUALITY FOR NONLINEAR HEAT EQUATION ON A SURFACE

  • Guo, Hongxin;Zhu, Chengzhe
    • 대한수학회보
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    • 제58권4호
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    • pp.909-914
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    • 2021
  • In this short note we prove new differential Harnack inequalities interpolating those for the static surface and for the Ricci flow. In particular, for 0 ≤ 𝜀 ≤ 1, α ≥ 0, 𝛽 ≥ 0, 𝛾 ≤ 1 and u being a positive solution to $${\frac{{\partial}u}{{\partial}t}}={\Delta}u-{\alpha}u\;{\log}\;u+{\varepsilon}Ru+{\beta}u^{\gamma}$$ on closed surfaces under the flow ${\frac{\partial}{{\partial}t}}g_{ij}=-{\varepsilon}Rg_{ij}$ with R > 0, we prove that $${\frac{\partial}{{\partial}t}}{\log}\;u-{\mid}{\nabla}\;{\log}\;u{\mid}^2+{\alpha}\;{\log}\;u-{\beta}u^{{\gamma}-1}+\frac{1}{t}={\Delta}\;{\log}\;u+{\varepsilon}R+{\frac{1}{t}{}\geq}0$$.

Generation of Discrete $G^1$ Continuous B-spline Ship Hullform Surfaces from Curve Network Using Virtual Iso-parametric Curves

  • Rhim, Joong-Hyun;Cho, Doo-Yeoun;Lee, Kyu-Yeul;Kim, Tae-Wan
    • Journal of Ship and Ocean Technology
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    • 제10권2호
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    • pp.24-36
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    • 2006
  • Ship hullform is usually designed with a curve network, and smooth hullform surfaces are supposed to be generated by filling in (or interpolating) the curve network with appropriate surface patches. Tensor-product surfaces such as B-spline and $B\'{e}zier$ patches are typical representations to this interpolating problem. However, they have difficulties in representing the surfaces of irregular topological type which are frequently appeared in the fore- and after-body of ship hullform curve network. In this paper, we proposed a method that can automatically generate discrete $G^1$ continuous B-spline surfaces interpolating given curve network of ship hullform. This method consists of three steps. In the first step, given curve network is reorganized to be of two types: boundary curves and reference curves of surface patches. Especially, the boundary curves are specified for their surface patches to be rectangular or triangular topological type that can be represented with tensor-product (or degenerate) B-spline surface patches. In the second step, surface fitting points and cross boundary derivatives are estimated by constructing virtual iso-parametric curves at discrete parameters. In the last step, discrete $G^1$ continuous B-spline surfaces are generated by surface fitting algorithm. Finally, several examples of resulting smooth hullform surfaces generated from the curve network data of actual ship hullform are included to demonstrate the quality of the proposed method.

500MSamples/s 6-비트 CMOS 폴딩-인터폴레이팅 아날로그-디지털 변환기 (A 500MSamples/s 6-Bit CMOS Folding and Interpolating AD Converter)

  • 이돈섭;곽계달
    • 한국정보통신학회논문지
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    • 제8권7호
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    • pp.1442-1447
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    • 2004
  • 본 논문에서는 HDD나 LAN 둥에 응용하기 위하여 아날로그 신호와 디지털 신호를 동시에 처리하는 VLSI의 내장용 회로로 사용하기에 적합한 CMOS 6-비트 폴딩-인터폴레이팅 AD 변환기를 설계하였다. 고속 데이터 통신에 사용하기 위하여 VLSI에 내장되는 아날로그 회로는 작은 칩의 크기와 적은 소비전력, 빠른 데이터 처리속도를 필요로 한다. 제안한 폴딩-인터폴레이팅 AD 변환기는 서로 다른 원리로 동작하는 2 개의 폴더를 캐스케이드로 결합하여 전압비교기와 인터폴레이션 저항의 개수를 현저히 줄일 수 있으므로 내장형 AD 변환기의 설계에 많은 장점을 제공한다 설계 공정은 0.25${\mu}m$ double-poly 2 metal n-well CMOS 공정을 사용하였다. 모의실험결과 2.5V 전원전압을 인가하고 500MHz의 샘플링 주파수에서 27mW의 전력을 소비하였으며 INL과 DNL은 각각 $\pm$0.lLSB, $\pm$0.15LSB이고 SNDR은 10MHz 입력신호에서 42dB로 측정되었다.

2단 구조를 사용한 250MS/s 8비트 CMOS 폴딩-인터폴레이팅 AD 변환기 (A 250MS/s 8 Bit CMOS folding and Interpolating AD Converter with 2 Stage Architecture)

  • 이돈섭;곽계달
    • 한국정보통신학회논문지
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    • 제8권4호
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    • pp.826-832
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    • 2004
  • 본 논문에서는 VLSI의 내장 회로로 사용하기에 적합한 CMOS 8 비트 폴딩-인터폴레이팅 AD 변환기를 설계하였다. 폴딩 AD 변환기의 비선형성을 개선하기 위하여 입력신호의 폴딩-인터폴레이팅에 의한 신호처리가 차례로 2 번 반복되는 2 단 구조를 사용하였다. 이 구조에서는 2 번째 폴딩 회로로서 트랜지스터 차동쌍을 이용한다. 2 단 폴딩 ADC는 디지틸 출력을 얻기 위한 전압비교기와 저항의 개수를 현저히 줄일 수 있으므로 칩 면적, 소비전력, 동작속도 둥에서 많은 장점을 제공한다. 설계공정은 0.25$\mu$m double-poly 2 metal n-well CMOS 공정을 사용하였다. 모의실험결과 2.5V 전원 전압을 인가하고 250MHz의 샘플링 주파수에서 45mW의 전력을 소비하였으며 INL과 DNL은 각 각 $\pm$0.2LSB, SNDR은 10MHz 입력신호에서 45dB로 측정되었다.