• Title/Summary/Keyword: hspice

Search Result 388, Processing Time 0.029 seconds

Design of Frequency to Analog-Voltage Converter (주파수-아날로그 전압 변환 회로의 설계)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.15 no.5
    • /
    • pp.1119-1124
    • /
    • 2011
  • The operation of current conveyor circuit is similar to an operational amplifier and a current conveyor circuit has the characteristics such as good linearity and stability. In this paper, a frequency-to-voltage converter circuit is designed by using a current conveyor circuit. The supply voltage is 5volts and the designed circuit is simulated by HSPICE. The range of the input frequency is from 4kHz to 200kHz. From the simulation results the error of the output voltages is less than from -1.3% to +2.5% compared to the calculated values.

A study on the Design of a High pass filter using single FTFN (한 개의 FTFN을 이용한 고역통과 필터의 설계)

  • 이영훈
    • Journal of the Korea Society of Computer and Information
    • /
    • v.7 no.3
    • /
    • pp.56-59
    • /
    • 2002
  • In this study, new serial and parallel resistor and capacitor-frequency-dependent negative resistance configurations are implemented that use one plus type four-terminal floating nullor(FTFN) and three passive components. The values of simulated elements can be orthogonally adjusted without any matching condition. High pass filter designed with this FTFN and AD844. Computer simulation was performed using the AD844 macro model by HSPICE. Simulated results agree well with theoretical values.

  • PDF

Max-based Analog Absolute Circuits with Small Error (작은 에러를 갖는 Max 회로 기반 아날로그 절대값 계산 회로)

  • Prasad sah, Maheshwar;Lin, Hai-Ping;Yang, Chang-Ju;Lee, Jun-Ho;Kim, Hyong-Suk
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.10 no.2
    • /
    • pp.248-255
    • /
    • 2009
  • Error is the major problem in communication system. Absolute circuit is one of the most important building blocks to implement for the error measurement in communication system as well as in analog circuit design. The main goal of this paper is to design a circuit with high accuracy and minimum error performance. In this paper, a new current mode absolute circuit is implemented to calculate the absolute value of two signals. This new design shows enhanced performance and low distortion over the previous implementation. The proposed circuit is simulated using Hspice and implemented in analog viterbi decoder. It is very suitable for implementing in error calculation for the large scale integrated circuit. Hspice simulation results of previous and new one circuit are reported.

Mixer using the direct-conversion method (직접 변환 방식을 이용한 주파수 혼합기)

  • Lim Chae-sung;Kim Sung-woo;Choi Hyek-Hwan;Lee Myoung-kyo;Kwon Tae-ha
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.9 no.6
    • /
    • pp.1269-1276
    • /
    • 2005
  • In this paper, Mixer using the direct-conversion method intended to use in front-end of a RF receiver is designed. The direct conversion Mixer is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for high integration, low power, and low cost. It operates at 2.4GHz band, and is designed and simulated with a 0.35um CMOS technology and HSPICE simulator. Layout is implemented with a Mentor IC Station. The 2.4GHz CMOS Mixer employs a modified single-balanced Gilbert Cell with additional MOSFET in the output stages to improve IIP2, which is a standard of linearity in direct conversion receiver. Additional coversion-stages's transconductances are controlled by each MOSFET's physical properties. The HSPICE simulation results show that the 2.4GHz CMOS Mixer has voltage gam of 29dB, IIP2 of 63dBm, respectively. The Mixer also draws 3.5mA from a 3.3V supply.

A Study on the Performance Variation of CNTFET SRAM by the Partial Density Change of Carbon Nanotubes (탄소나노튜브 부분 밀도 변화에 의한 CNTFET SRAM 성능 변화에 대한 연구)

  • Cho, Geunho
    • Journal of IKEEE
    • /
    • v.26 no.1
    • /
    • pp.83-88
    • /
    • 2022
  • With high performance and wide application, a CNTFET has been attracting a lot of attention as a next-eneration semiconductor, but the manufacturing process of CNTFET has not been mature enough, which makes commercialization difficult. In order to overcome the imperfections of the CNTFET manufacturing process and to increase the possibility of commercialization, this paper analyzes the CNTFET SRAM performance variation according to the CNTFET partial density change based on the recently reported CNTFET manufacturing process. Through HSPICE circuit simulation analysis using the existing 32nm CNTFET HSPICE library file, transistors whose performance variation is less sensitive to partial CNT density are selected among the six transistors constituting the SRAM cell and acceptable CNT density range is proposed. As the result of analysis, it is found that when the CNT density of the two transistors connected to the bit line in SRAM cell changed from 6/32nm to 8/32nm, the deviation of SRAM performance is less than 9% and when the CNT density is less than 5/32nm, the SRAM delay is increased by more than 8 time.

Dynamic Digital Logic Style for LTPS TFT Based System-On-Panel Application

  • Kim, Jae-Geun;Jeong, Je-Young
    • 한국정보디스플레이학회:학술대회논문집
    • /
    • 2004.08a
    • /
    • pp.446-449
    • /
    • 2004
  • We developed a dynamic logic architecture which resulted better leakage current, lower power consumption and less area compared to the conventional dynamic logic structures. We demonstrated the advantage from HSPICE simulation and test chip design has been completed.

  • PDF

Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs (통계적으로 최적화된 비동기식 가변길이코덱용 배럴 쉬프트)

  • Peter A. Beerel;Kim, Kyeoun-Soo
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.28 no.11A
    • /
    • pp.891-901
    • /
    • 2003
  • This paper presents low-power asynchronous barrel shifters for variable length encoders and decoders useful in portable applications using multimedia standards. Our approach is to create multi-level asynchronous barrel shifters optimized for the skewed shift control statistics often found in these codecs. For common shifts, data passes through one level, whereas for rare shifts, data passes though multiple levels. We compare our optimized designs with the straightforward asynchronous and synchronous designs. Both pre- and Post-layout HSPICE simulation results indicate that, compared to their synchronous counterparts, our designs provide over a 40% savings in average energy consumption for a given average performance.

Test Method of an Embedded CMOS OP-AMP (내장된 CMOS 연산증폭기의 테스트 방법)

  • 김강철;송근호;한석붕
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.7 no.1
    • /
    • pp.100-105
    • /
    • 2003
  • In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

Phase Locked Loop with Analog Band-Selection Loop (아날로그 부대역 선택 루프를 이용한 위상 고정 루프)

  • Lee, Sang-Ki;Choi, Young-Shig
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.49 no.8
    • /
    • pp.73-81
    • /
    • 2012
  • In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter (2차-RC 필터와 Sample-Hold 커패시터로 구성된 루프 필터와 단방향 전하펌프를 가진 PLL)

  • Baek, Seung-Ha;Choi, Young-Shig
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.10
    • /
    • pp.2380-2386
    • /
    • 2013
  • A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.