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http://dx.doi.org/10.7471/ikeee.2022.26.1.83

A Study on the Performance Variation of CNTFET SRAM by the Partial Density Change of Carbon Nanotubes  

Cho, Geunho (Dept. of Electronic Engineering, Seokyeong University)
Publication Information
Journal of IKEEE / v.26, no.1, 2022 , pp. 83-88 More about this Journal
Abstract
With high performance and wide application, a CNTFET has been attracting a lot of attention as a next-eneration semiconductor, but the manufacturing process of CNTFET has not been mature enough, which makes commercialization difficult. In order to overcome the imperfections of the CNTFET manufacturing process and to increase the possibility of commercialization, this paper analyzes the CNTFET SRAM performance variation according to the CNTFET partial density change based on the recently reported CNTFET manufacturing process. Through HSPICE circuit simulation analysis using the existing 32nm CNTFET HSPICE library file, transistors whose performance variation is less sensitive to partial CNT density are selected among the six transistors constituting the SRAM cell and acceptable CNT density range is proposed. As the result of analysis, it is found that when the CNT density of the two transistors connected to the bit line in SRAM cell changed from 6/32nm to 8/32nm, the deviation of SRAM performance is less than 9% and when the CNT density is less than 5/32nm, the SRAM delay is increased by more than 8 time.
Keywords
SRAM; CNTFET; CNT; CNT Density; Cache;
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Times Cited By KSCI : 5  (Citation Analysis)
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