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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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A Study on the Performance Variation of CNTFET SRAM by the Partial Density Change of Carbon Nanotubes

탄소나노튜브 부분 밀도 변화에 의한 CNTFET SRAM 성능 변화에 대한 연구

  • Cho, Geunho (Dept. of Electronic Engineering, Seokyeong University)
  • Received : 2022.03.02
  • Accepted : 2022.03.28
  • Published : 2022.03.31
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Abstract

With high performance and wide application, a CNTFET has been attracting a lot of attention as a next-eneration semiconductor, but the manufacturing process of CNTFET has not been mature enough, which makes commercialization difficult. In order to overcome the imperfections of the CNTFET manufacturing process and to increase the possibility of commercialization, this paper analyzes the CNTFET SRAM performance variation according to the CNTFET partial density change based on the recently reported CNTFET manufacturing process. Through HSPICE circuit simulation analysis using the existing 32nm CNTFET HSPICE library file, transistors whose performance variation is less sensitive to partial CNT density are selected among the six transistors constituting the SRAM cell and acceptable CNT density range is proposed. As the result of analysis, it is found that when the CNT density of the two transistors connected to the bit line in SRAM cell changed from 6/32nm to 8/32nm, the deviation of SRAM performance is less than 9% and when the CNT density is less than 5/32nm, the SRAM delay is increased by more than 8 time.

높은 성능과 폭넓은 활용성으로 CNTFET은 차세대 반도체로 많은 관심을 받아 왔으나 생산 공정이 아직 충분히 성숙되지 않아 상용화에 어려움을 겪어 왔다. 이러한 CNTFET 공정의 불완전성을 극복하고 상용화 가능성을 높이기 위해 본 논문에서는 최근 발표된 CNTFET 공정 내용을 참고하여 CNTFET 부분 밀도 변화에 따른 CNTFET SRAM 성능 변화에 대해 분석하고자 한다. 현존하는 32nm CNTFET HSPICE용 라이브로리 파일을 활용한 HSPICE 회로 시뮬레이션 분석을 통해 SRAM 셀을 구성하는 6개의 트랜지스터 중, CNT 밀도 변화에 대해 성능 변화가 덜 민감한 트랜지스터를 선택하고, 허용되는 CNT 밀도 범위를 제안하였다. 분석 결과, SRAM 내 비트라인에 연결된 2개의 트랜지스터의 CNT 밀도가 6/32nm에서 8/32nm로 변경되더라도 SRAM 성능 편차는 9% 이하인 것으로 나타나고 CNT 밀도가 5/32nm 미만인 경우 SRAM 지연이 약 8배 이상 증가됨을 알 수 있었다.

Keywords

Acknowledgement

The EDA tool was supported by the IC Design Education Center(IDEC), Korea

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