• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.749-752
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• 2014

The device performance of n-channel MuGFET with different fin width, existence of spacer and channel length has been characterized. Tri-Gate structure(fin number=10) has been used. There are four kinds of Tri-Gate with fin width=55nm with spacer, fin width=70nm with spacer, fin width=55nm without spacer, fin width=70nm without spacer. DIBL, subthreshold swing, Vt roll-off, (above Short Channel Effect)and hot carrier stress degradation have been measured. From the experiment results, short Channel Effect with spacer was decreased, hot carrier degradation with spacer and narrow fin width was decreased. Therefore, layout of LDD structure with spacer and narrow fin width is desirable in short channel effect and hot carrier degradation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.12
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• pp.3626-3631
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• 2009

This study has provided some of the first experimental results of NMOSFET hot-carrier degradation for the analog circuit application. After hot-carrier stress under the whole range of gate voltage, the degradation of NMOSFET characteristics is measured in saturation region. In addition to interface states, the evidences of hole and electron traps are found near drain depending on the biased gate voltage, which is believed to the cause for the variation of the transconductance($g_m$) and the output conductance($g_{ds}$). And it is found that hole trap is a dominant mechanism of device degradation in a low-gate voltage saturation region, The parameter degradation is sensitive to the channel length of devices. As the channel length is shortened, the influence of hole trap on the channel conductance is increased. Because the magnitude of $g_m$ and $g_{ds}$ are increased or decreased depending on analog operation conditions and analog device structures, careful transistor design including the level of the biased gate voltage and the channel length is therefore required for optimal voltage gain ($A_V=g_m/g_{ds}$) in analog circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.199-200
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• 2005

In this paper, the electrical characteristics and hot-carrier induced electrical performance degradations of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated. Different from the low voltage CMOS device, the only specific on-resistance was degraded due to hot-carrier stressing in LDMOS transistor. However, other electrical parameters such as threshold voltage, transconductance, and saturated drain current were not degraded after stressing. The amount of on-resistance degradation of LDMOS transistor that was implanted n-well with $1.0\times10^{13}/cm^2$ was approximately 1.6 times more than that of LDMOS transistor implanted n-well with $1.0\times10^{12}/cm^2$. Similar to low voltage CMOS device, the peak on-resistance degradation in LDMOS device was observed at gate voltage of 2.2V while the drain applied voltage was 50V. It means that the maximum impact ionization at the drain junction occurs at the gate voltage of 2.2V applying the drain voltage of 50V.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.365-368
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• 2002

WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.243-246
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• 1999

We studied the MOSFET characteristics and the hot-carrier reliability with the sidewall spacer composition and the post gate oxidation thickness in 0.20${\mu}{\textrm}{m}$ gate length transistor. The MOSFET with NO(Nitride＋Oxide) sidewall spacer exhibits the large degradation of hot-carrier lifetime because there is no buffering oxide against nitride stress. When the post gate oxidation is skipped, the hot-carrier lifetime is improved, but GIDL (Gate Induced Drain Leakage) current is also increased.

• 전자공학회논문지 IE
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• v.47 no.1
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• pp.1-5
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• 2010

This paper presents new results of the impact of gate structure on hot-carrier-induced performance degradation in SOI low noise amplifier. Circuit simulations were carried out using the measured S-parameters of H--gate and T-gate SOI MOSFETs and Agilent's Advanced Design System (ADS) to compare the performance of H-gate LNA and T-gate LNA before and after stress. We will discuss the figure of merit for the characterization of low noise amplifier in terms of impedance matching (S11), noise figure, and gain as well as the relation between device degradation and performance degradation of LNA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.13-18
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• 2007

This paper presents the experimental findings on the different degradation mechanism which depends on the gate oxide thickness in lateral DMOS transistors. For thin oxide devices, the generation of interface states in the channel region and the trapped holes in the drift region is found to be the causes of the device degradation. For thick devices, the generation of interface states in the channel region is found to be the causes of the device degradation. We confirmed the different degradation mechanism using device simulation. From the comparison of device degradation under DC and AC stress, it is found that the device degradation is more significant under DC stress than one under AC stress. The device degradation under AC stress is more significant in high frequency. Therefore the hot carrier induced degradation should be more carefully considered in the design of RF LDMOS transistors and circuit design.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.53-58
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• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

• 전자공학회논문지 IE
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• v.45 no.2
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• pp.1-5
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• 2008

In this work, RF performance degradation due to hot carrier effects in SOI MOSFET have been measured and analyzed. The LNA that designed at $V_{GS}=0.8V$, f=2.5GHz, gain is 16.51dB and noise figure is 1.195dB. After stress at SOI, the LNA's gain and noise figure change of 15.3dB and 1.44dB with before stress.