• 한국정보통신학회논문지
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• 제22권1호
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• pp.117-124
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• 2018

박막 두께가 다른 무접합 비정질 InGaZnO 막막 트랜지스터를 제작하고 박막 두께, 동작 온도 및 빛의 세기에 따른 소자의 성능 변수를 추출하고 게이트 산화층 항복전압을 분석하였다. 박막의 두께가 클수록 소자의 성능이 우수하나 드레인 전류의 증가로 게이트 산화층 항복전압은 감소하였다. 고온에서도 소자의 성능은 개선되었으나 게이트 산화층 항복 전압은 감소하였다. 빛의 세기가 증가할수록 광자에 의해 생성된 전자로 드레인 전류는 증가 하였으나 역시 게이트 산화층 항복전압은 감소하였다. 박의 두께가 클수록, 고온일수록, 빛의 세기가 강할수록 채널의 전자수가 증가하여 산화층으로 많이 주입되었기 때문이다. 무접합 a-IGZO 트랜지스터를 BEOL 트랜지스터로 사용하기 위해서는 박막 두께 및 동작 온도를 고려해서 산화층 두께를 설정해야 됨을 알 수 있었다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.176-176
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• 2003

The effects of oxide thickness and gate length of MgO/GaN metal oxide semiconductor field effect transistors (MOSFETs) on I-V, threshold voltage and breakdown voltage characteristics were examined using a drift-diffusion model. The saturation drain current scales in an inverse logarithmic fashion with MgO thickness and is < 10$^{-3}$ A.${\mu}{\textrm}{m}$$^{-1}$ for 0.5 ${\mu}{\textrm}{m}$ gate length devices with oxide thickness > 600 $\AA$ or for all 1 ${\mu}{\textrm}{m}$ gate length MOSFETs with oxide thickness in the range of >200 $\AA$. Gate breakdown voltage is > 100 V for gate length >0.5 ${\mu}{\textrm}{m}$ and MgO thickness > 600 $\AA$. The threshold voltage scales linearly with oxide thickness and is < 2 V for oxide thickness < 800 $\AA$ and gate lengths < 0.6 ${\mu}{\textrm}{m}$. The GaN MOSFET shows excellent potential for elevated temperature, high speed applications.

• 전자공학회논문지A
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• 제33A권12호
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• pp.77-82
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• 1996

The breakdown characteristics of metal-oxide-semiconductor(MOS) capacitors fabricated by Al, polysilicon, and tungsten polycide gate electrodes onto gate oxide was evaluated by time zero dielectric breakdwon (TZDB). The average breakdown field of the gate oxide with tungsten polycide electride was lower than that of the polysilicon electrode. The B model (1~8MV/cm) failure of the gate oxide with tungsten polycide electrode was increased with increasing annealing temperature in the dry $O_{2}$ ambient. This is attributed ot fluorine and tungsten diffusion from thungsten silicide film into the gate oxide, and stress increase of tungsten polcide after annealing treatment.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권2호
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• pp.63-68
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• 2003

The DC and RF characteristics of $In_{0.5}Ga_{0.5}P/In_{0.22}Ga_{0.78}As/GaAs$ p-HEMTs with a gate oxide layer of various thicknesses ($50{\;}{\AA},{\;}300{\;}{\AA}$) were investigated and compared with those of a Schottky-gate p-HEMT without the gate oxide layer. A prominent improvement in the breakdown voltage characteristics were observed for a p-HEMT having a gate oxide layer, which was implemented by using a liquid phase oxidation technique. The on-state breakdown voltage of the p-HEMT having the oxide layer of $50{\;}{\AA}$was ~2.3 times greater than that of a Schottky-gate p-HEMT. However, the p-HEMT having the gate oxide layer of $300{\;}{\AA}$ suffered from a poor gate-control capability due to the drain induced barrier lowering (DIBL) resulting from the thick gate oxide inspite of the lower gate leakage current and the higher on-state breakdown voltage. The results for a primitive p-HEMT having the gate oxide layer without any optimization of the structure and the process indicate the potential of p-HEMT having the gate oxide layer for high-power applications.

• 대한전자공학회논문지SD
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• 제41권8호
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• pp.1-8
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• 2004

두께가 3nm인 게이트 산화막을 사용한 n-MOSFET에 정전압 스트레스를 가하였을 때 관찰되는 SILC 및 soft breakdown 열화 및 이러한 열화가 소자 특성에 미치는 영향에 대해 실험하였다. 열화 현상은 인가되는 게이트 전압의 극성에 따라 그 특성이 다르게 나타났다. 게이트 전압이 (-)일 때 열화는 계면 및 산화막내 전하 결함에 의해 발생되었지만, 게이트 전압이 (＋)일 때는 열화는 주로 계면 결함에 의해 발생되었다. 또한 이러한 결함의 생성은 Si-H 결합의 파괴에 의해 발생할 수 있다는 것을 중수소 열처리 및 추가 수소 열처리 실험으로부터 발견하였다. OFF 전류 및 여러 가지 MOSFET의 전기적 특성의 변화는 관찰된 결함 전하(charge-trapping)의 생성과 직접적인 관련이 있다. 그러므로 실험 결과들로부터 게이트 산화막으로 터널링되는 전자나 정공에 의한 Si 및 O의 결합 파괴가 게이트 산화막 열화의 원인이 된다고 판단된다. 이러한 물리적 해석은 기존의 Anode-Hole Injection 모델과 Hydrogen-Released 모델의 내용을 모두 포함하게 된다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.970-973
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• 1999

When the size of the device is decreased, the hot carrier degradation presents a severe problem for long-term device reliability. In this paper we fabricated & tested the 0.26${\mu}{\textrm}{m}$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the characteristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve and charge trapping using the Hp4145 device tester As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially a hot carrier lifetime(nitride oxide gate device satisfied 30years, but the lifetime of wet gate oxide was only 0.1year), variation of Vg, charge to breakdown and charge trapping etc.

• 한국전기전자재료학회논문지
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• 제16권12호
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 정보처리학회논문지A
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• 제15A권4호
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• pp.211-216
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• 2008

본 논문에서는 핫 케리어 효과, 항복전압 전하, 트랜지스터 Id Vg 특성곡선, 전하 트래핑, SILC와 같은 특성들을 비교하기 위하여 HP 4145 디바이스 테스터를 사용하여 습식 산화막과 질화 산화막으로된 $0.2{\mu}m$ NMOSFET를 만들어 측정하였다. 그 결과 질화 산화막으로 만들어진 디바이스가 핫 케리어 수명(질화 산화막은 30년 이상인 반면에 습식 산화막 소자는 0.1년임), Vg의 변화, 항복전압, 전계 시뮬레이션, 전하 트래핑면에서도 습식 산화막 소자보다 우수한 결과를 얻을 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.205-210
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• 2003

A 3-Transistor cell CMOS OTP ROM array using standard CMOS antifuse (AF) based on permanent breakdown of MOSFET gate oxide is proposed, fabricated and characterized. The proposed 3-T OTP cell for ROM array is composed of an nMOS AF, a high voltage (HV) blocking nMOS, and cell access transistor, all compatible with standard CMOS technology. The experimental results show that the proposed structure can be a viable technology option as a high density OTP ROM array for modern digital as well as analog circuits.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.74-75
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• 2008

TIGBT has some merits which are lower on-state voltage drop and smaller cell pitch, but also has a defect which is relatively lower breakdown voltage in comparison with planar IGBT. This lower breakdown voltage is due to the electric field which is concentrated on beneath the vertical gate. Therefore in this paper, new trench IGBT structure is proposed to improve breakdown voltage In the new proposed structure, a narrow oxide beneath the trench gate edge where the electric field is concentrated is extended into rectangular shape to decrease the electric field. As a result, breakdown voltage is improved to 23%.