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Trap Generation during SILC and Soft Breakdown Phenomena in n-MOSFET having Thin Gate Oxide Film  

이재성 (위덕대학교 정보통신공학부)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.8, 2004 , pp. 1-8 More about this Journal
Abstract
Experimental results are presented for gate oxide degradation, such as SILC and soft breakdown, and its effect on device parameters under negative and positive bias stress conditions using n-MOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both interface and oxide bulk traps are found to dominate the reliability of gate oxide. However, for positive gate voltage, the degradation becomes dominated mainly by interface trap. It was also found the trap generation in the gate oxide film is related to the breakage of Si-H bonds through the deuterium anneal and additional hydrogen anneal experiments. Statistical parameter variations as well as the “OFF” leakage current depend on both electron- and hole-trapping. Our results therefore show that Si or O bond breakage by tunneling electron and hole can be another origin of the investigated gate oxide degradation. This plausible physical explanation is based on both Anode-Hole Injection and Hydrogen-Released model.
Keywords
SILC; soft breakdown; interface trap; oxide trap; deuterium;
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