• Journal of the Korean Ceramic Society
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• v.41 no.9
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• pp.637-641
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• 2004

We investigated the effects of SiH$_4$ gas on the surface of Hf-silicate films during the deposition of polycrystalline (poly) Si films and the thermal stability of sputtered Hf-silicate films in poly Si/Hf-silicate structure by using High Resolution Transmission Electron Microscopy (HR-TEM) and X-ray Photoelectron Spectroscopy (XPS). Hf-silicate films were deposited by using DC-mag-netron sputtering with Hf target and Si target and poly Si films were deposited at 600$^{\circ}C$ by using Low Pressure Chemical Vapor Deposition (LPCVD) with SiH$_4$ gas. After poly Si film deposition at 600$^{\circ}C$, Hf silicide layer was observed between poly Si and Hf-silicate films due to the reaction between active SiH$_4$ gas and Hf-silicate films. After annealing at 900$^{\circ}C$, Hf silicide, formed during the deposition of poly Si, changed to Hf-silicate and the phase separation of the silicate was not observed. In addition, the Hf-silicate films remain amorphous phase.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1284-1287
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• 2007

Titanium dioxide ($TiO_2$) is promising candidate for fabricating blocking layer of gate dielectrics in non-volatile memory (NVM). In this work, we investigated $TiO_2$ as high dielectric constant material instead of silicon dioxide ($SiO_2$), which is generally used as blocking layer for NVM.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.70-73
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• 2001

MFIS(Metal-ferroelectric-insulator- semiconductor) structures using silicon oxynitride(SiON) buffer layers were fabricatied and demonstrated nonvolatile memory operations. Oxynitride(SiON) films have been formed on p-Si(100) by RTP(rapid thermal process) in O$_2$+N$_2$ ambient at 1100$^{\circ}C$. The gate leakage current density of Al/SiON/Si(100) capacitor was about the order of 10$\^$-8/ A/cm$^2$ at the range of ${\pm}$ 2.5 MV/cm. The C-V characteristics of Al/LiNbO$_3$/SiON/Si(100) capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 24. The memory window width was about 1.2V at the electric field of ${\pm}$300 kV/cm ranges.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.198-201
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• 2006

The optimization of poly-Si TFT process on metal foil for UTL AMOLED was systematically investigated. The improvement in device performance of poly-Si TFT on metal foil was achieved by optimizing the dopant activation condition and gate dielectric structure. Hence, the world first flexible full color 5.6-inch AMOLED with top emission mode on poly-Si TFT stainless steel foil is demonstrated.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.309-313
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• 2006

We demonstrated 2.2inch qqVGA AMOLED display drived by ultra low temperature poly-Si (ULTPS) TFT not transferred but direct fabricated below $200^{\circ}C$. Si channel was crystallized by decreasing impurity concentration even at room temperature. Gate insulator with a breakdown field exceeding 8 MV/cm was realized by Inductively coupled plasma - CVD. In order to reduce stress of plastic, organic film was coated as inter-dielectric and passivation layers. Finally, ULTPS TFT of which mobility is over $20cm^2/Vsec$ was fabricated on transparent plastic substrate and drived OLED display successfully.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.04b
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• pp.45-48
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• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.

• Transactions on Electrical and Electronic Materials
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• v.8 no.3
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• pp.139-142
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• 2007

Organic field-effect transistor (FET) based on a copper Phthalocyanine (CuPc) material as an active layer and a $SiO_2$ as a gate insulator were fabricated and analyzed. We measured the typical FET characteristics of CuPc in air. The electrical characteristics of the CuPc FET device were analyzed by a Maxwell-Wagner model. The Maxwell-Wagner model employed in analyzing double-layer dielectric system was helpful to explain the C-V and I-V characteristics of the FET device. In order to further clarity the channel formation of the CuPc FET, optical second harmonic generation (SHG) measurement was also employed. Interestingly, SHG modulation was not observed for the CuPc FET. This result indicates that the accumulation of charge from bulk CuPc makes a significant contribution.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.7
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• pp.521-524
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• 2012

We report on variations of electrical properties with different active layer thickness and post-annealing temperature in amorphous In-Ga-Zn-O (IGZO) thin-film transistors (TFTs). In particular, subthreshold swing (SS) of the IGZO-TFTs was improved as increasing the active layer thickness at an given post-annealing temperature, accompanying the negative shift in turn-off voltage. However, as increasing post-annealing temperature, only turn-off voltage was shifted negatively with almost constant SS value. The effect of the active layer thickness and post-annealing temperature on electrical properties, such as SS, field effect mobility and turn-off voltage in IGZO-TFTs has been explained in terms of the variation of trap density in IGZO channel layer and at gate dielectric/IGZO interface.