• Journal of information and communication convergence engineering
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• v.8 no.1
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• pp.107-111
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• 2010

This paper has presented the dependence of the threshold voltage on back gate bias and drain voltage for FinFET. The FinFET has three gates such as the front gate, side and back gate. Threshold voltage is defined as the front gate bias when drain current is 1 micro ampere as the onset of the turn-on condition. In this paper threshold voltage is investigated into the analytical potential model derived from three dimensional Poisson's equation with the variation of the back gate bias and drain voltage. The threshold voltage of a transistor is one of the key parameters in the design of CMOS circuits. The threshold voltage, which described the degree of short channel effects, has been extensively investigated. As known from the down scaling rules, the threshold voltage has been presented in the case that drain voltage is the 1.0V above, which is set as the maximum supply voltage, and the drain induced barrier lowing(DIBL), drain bias dependent threshold voltage, is obtained using this model.

• Progress in Superconductivity
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• v.13 no.1
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• pp.47-51
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• 2011

Mono-atomic-layer graphene is an interesting system for studying the relativistic carrier transport arising from a linear energy-momentum dispersion relation. An easy control of the carrier density in graphene by applying an external gate field makes the system even more useful. In this study, we measured the Josephson current in a device consisting of mono-layer graphene sheet sandwiched between two closely spaced (~300 nm) aluminum superconducting electrodes. Gate dependence of the supercurrent in graphene Josephson junction follows the gate dependence of the normal-state conductance. The gate-tunable and relatively large supercurrent in a graphene Josephson junction would facilitate our understanding on the weak-link behavior in a superconducting-normal metal-superconducting (SNS) type Josephson junction.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.586-591
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• 2004

We studied the dependence of hot-tarrier-induced degradation characteristics on nitrogen concentration in NO(Nitrided-Oxide) gate of nMOS, under ac and dc stresses. The $\Delta$V$_{t}$ and $\Delta$G$_{m}$ dependence of nitrogen concentration were observed, We observed that device degradation was suppressed significantly when the nitrogen concentration in the gate was increased. Compared to $N_2$O oxynitride, NO oxynitride gate devices show a smaller sensitivity to ac stress frequency. Results suggest that the improved at-hot carrier immunity of the device with NO gate may be due to the significantly suppressed interface state generation and neutral trap generation during stress.ess.

• ETRI Journal
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• v.44 no.3
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• pp.504-511
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• 2022

Monte Carlo simulations show that, as temperature increases, the average kinetic energy of channel electrons in a GaN transistor first decreases and then increases. According to the calculations, the relative energy change reaches 40%. This change leads to a reduced barrier height due to quantum coupling among the three-dimensional motions of channel electrons. Thus, an analysis and physical model of the gate leakage current that includes drift velocity is proposed. Numerical calculations show that the negative and positive temperature dependence of gate leakage currents decreases across the barrier as the field increases. They also demonstrate that source-drain voltage can have an effect of 1 to 2 orders of magnitude on the gate leakage current. The proposed model agrees well with the experimental results.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.1119-1122
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• 2000

This paper describes on RF circuit simulation technique, especially on a RF modeling and a model extraction of a LDMOS(Lateral Diffused MOS) that has gate-width (Wg) dependence. Small-signal model parameters of the LDMOSs with various gate-widths extracted from S-parameter data are applied to make the relation between the RF performances and gate-width. It is proved that a source inductance (Ls) was not applicable to scaling rules. These extracted small-signal model parameters are also utilized to remove extrinsic elements in an extraction of a large-signal model (using HP Root MOSFET Model). Therefore, we can omit an additional measurement to extract extrinsic elements. When the large-signal model with Ls having the above gate-width dependence is applied to a high-power LDMOS module, the simulated performances (Output power, etc.) are in a good agreement with experimental results. It is proved that our extracted model and RF circuit simulation have a good accuracy.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.805-810
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• 2016

The dependence of drain induced barrier lowering(DIBL) is analyzed for doping concentration in channel of asymmetric double gate(DG) MOSFET. The DIBL, the important short channel effect, is described as lowering of source barrier height by drain voltage. The analytical potential distribution is derived from Poisson's equation to analyze the DIBL, and the DIBL is observed according to top/bottom gate oxide thickness and bottom gate voltage as well as channel doping concentration. As a results, the DIBL is significantly influenced by channel doping concentration. DIBL is significantly increased by doping concentration if channel length becomes under 25 nm. The deviation of DIBL is increasing with increase of oxide thickness. Top and bottom gate oxide thicknesses have relation of an inverse proportion to sustain constant DIBL regardless channel doping concentration. We also know the deviation of DIBL for doping concentration is changed according to bottom gate voltage.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.113-117
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• 2007

We have investigated the effects of doping concentration in polysilicon floating gate on the endurance characteristics of the EEPROM cell haying the structure of spacer select transistor. Several samples were prepared with different implantation conditions of phosphorus for the floating gate. Results show the dependence of doping concentration in polysilicon floating gate on performance of EEPROM cell from the floating gate engineering point of view. All of the samples were endured up to half million programming/erasing cycle. However, the best $program-{\Delta}V_{T}$ characteristic was obtained in the cell doped at the dose of $1{\times}10^{15}/cm^{2}$.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.248-252
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• 2004

본 연구에서는 새로 고안된 NOT 논리를 포함한 방전 AND gate의 방전특성에 대해 고찰하고 동작 특성을 해석하였다. 새로 고안된 방전 AND gate는 방전 경로에 따른 전극사이의 전압의 변화로 AND 출력을 유도한다. 측정결과 AND 출력은 A전극의 A1전압과 B전극 전압의 상호 관계에 영향을 받는다는 것을 알았다. 또한 AND 출력을 위한 DC priming 방전은 방전 후 $30{\mu}s$ 정도까지 영향을 미치며 방전 강도는 AND gate의 특성에 영향을 주지 않는다는 것을 알았다. 시험결과를 통해 AND gate를 구성하는 각 전극 전압의 최적 값을 얻었으며 기존의 연구 결과보다 안정적인 AND 동작을 확인하였다.