• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1226-1227
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• 2008

In this study, a single p-type Si nanowire - Au nanoparticles nano floating gate memory (NFGM) device is successfully fabricated and characterized their memory effects by comparison of electrical characteristics of p-type Si nanowire-based field effect transistor (FET) devices with Au nanoparticles embedded in the $Al_2O_3$ gate materials and without the Au nanoparticles. Drain current versus gate voltage ($I_{DS}-V_{GS}$) characteristics of a single p-type Si nanowire - Au nanoparticle NFGM device show counterclockwise hysteresis loops with the threshold voltage shift of ${\Delta}V_{th}$= 3.0 V. However, p-type Si nanowire based top-gate device without Au nanoparticles does not exhibit a threshold voltage shift. This behavior is ascribed to the presence of the Au nanoparticles, and is indicative of the trapping and emission of electrons in the Au nanoparticles.

• 한국산학기술학회논문지
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• 제15권8호
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• pp.5213-5218
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• 2014

유기메모리 제작을 위해 플라즈마 중합법에 의해 절연박막, 터널링 박막을 제작하였고, Au 메모리박막을 이용하여 플로팅게이트형 유기메모리를 제작하였다. 플로팅 게이트형 유기메모리의 메모리층의 전하충전 및 방전에 따른 유기메모리 동작특성을 생각해 보았고, 이를 증명하고자 게이트전압에 따른 히스테리전압 및 메모리전압을 측정하였다. 그 결과 게이트 전압의 인가에 따른 메모리층의 동작 이론을 증명하고자 게이트전압이 증가함에 따른 소스-드레인 전류의 히스테리시스 현상이 심해지는 것을 확인하였고, -60~60[V]전압 인가시 26[V]의 큰 히스테리시스 전압값을 보였다. 또한 게이트 전극에 쓰기전압인가에 따른 현상을 본 결과, 60[V]의 쓰기 전압을 인가하였을 시 13[V]의 memory 전압을 나타내었고, 80[V]의 쓰기전압을 인가하였을 시 18[V]로 memory 전압이 약 40[%] 향상된 수치를 보였다. 이로부터 메모리층의 전하 충전 및 방전에 따른 메모리 동작특성 이론을 실험적으로 검증하였다.

• Journal of Electrical Engineering and information Science
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• 제2권3호
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• 전기전자학회논문지
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• 제21권2호
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• pp.150-153
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• 2017

본 논문에서는 Floating기술을 이용한 GCNMOS 기반의 ESD(Electrostatic Discharge)보호회로를 제안한다. 제안된 보호회로의 특성 분석을 위해서 시놉시스사의 TCAD 시뮬레이션을 이용하였으며 기존의 GGNMOS, GCNMOS와 비교 분석하였다. 제안된 보호회로는 Gate coupling과 Body floating기술을 적용하였으며 기존 ESD보호회로인 GGNMOS, GCNMOS와 비교하여 더 낮은 4.86V의 트리거 전압 및 1.47ns의 짧은 턴-온 타임 특성을 갖는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권2호
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• pp.101-105
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• 2006

Nanoscale floating-gate characteristic of colloidal Au nanoparticles electrostatically assembled on the oxidized surface of Si nanowires have been investigated. The Si nanowire split-gate transistor structure was fabricated by electron beam lithography and subsequent reactive ion etching. Colloidal Au nanoparticles with ${\sim}5$ nm diameters were selectively deposited onto the Si nanowire surface by 2 min electrophoresis. It was found that electric fields applied to the self-aligned split side gates allowed charge to be transferred on the Au nanoparticles. It was observed that the depletion mode cutoff voltage, induced by the self-aligned side gates, was shifted by more than 1 V after Au nanoparticle electrophoresis. This may be due to the semi-one dimensional nature of the narrow Si nanowire transport channel, having much enhanced sensitivity to charges on the surface.

• 전자공학회지
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• 제32권2호
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• pp.44-52
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• 2005

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권6호
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• pp.267-273
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• 2003

The plasma display panel with the electrode structure of new discharge AND gate and its driving scheme were proposed and the driving system for experiment was developed. And operation of these discharge AND gate was verified by the experiment of PDP addressing with floating electrode. This discharge AND gate operated by the operation speed of 8$mutextrm{s}$ and the operation margin of 100V. The address operation margin of 10V also obtained. It was known to be able to control the discharge of the adjoining scan electrode accurately. Because proposed method uses the DC discharge the control of the discharge can be facilitated compared with conventional discharge AND gate. Moreover, because the input discharge and the output discharge of discharge gate are separate, the display discharge can be prevented from passing discharge gates. Therefore, it is possible to apply to the large screen plasma display panel. And the decrease of contrast ratio does not occur because the scanning discharge does not influence the picture quality.

• 조명전기설비학회논문지
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• 제18권5호
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• pp.42-47
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• 2004

본 연구는 기존에 제안한 방전 AND gate PDP의 문제점을 개선한 연구결과로서 AND gate를 구성하는 DC 방전의 극성을 반대로 설계하여 인접 주사전극에 대한 cross talk 문제를 개선하였다. 또한 기존의 AND gate의 동작이 공간전하에 의한 방전의 비선형성에 의존한 것과는 달리 본 연구에서 제안한 AND gate는 방전 회로에 따라 인가전압이 변화하는 것을 이용한 NOT 논리를 AND gate에 부가하여 동작이 한층 안정해 졌다. 실험 결과4개의 수평 주사전극에 대해 선택적인 어드레스 방전이 가능하였으며 각각 34V와 70V의 AND 방전 및 Data 방전의 동작마진을 얻을 수가 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.14-15
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• 2009

Insulated Gate Bipolar Transistor(IGBTs) are widely used in power device industry. However, to improve the breakdown voltage, IGBTs are suffered from increasing on-state voltage drop due to structural design. In this paper, the new structure is proposed to solve this problem. The proposed structure has double p-floating layer inserted in n-drift layer. The p-floating layers improve the breakdown voltage compared to conventional IGBT without change of other electrical characteristics such as on-state voltage drop and threshold voltage. this is because the p-floating layers expand electric field distribution at blocking state. A electrical characteristic of proposed structure is analyzed by using simulators such as TSUPREM and MEDICI. As a result, on-state voltage drop and threshold voltage are same to a conventional TIGBT, but breakdown voltage is improved to 16%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.545-548
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• 1998

Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.